MPAMBW3

Enables software to configure a maximum fraction of memory bandwidth that the PE is permitted to use when executing at EL3 with its current PARTID.

Configuration

This register is present only when FEAT_MPAM_PE_BW_CTRL is implemented. Otherwise, direct accesses to MPAMBW3_EL3 are UNDEFINED.

Attributes

Field descriptions

HW_SCALE_ENABLE, bit [63]
When MPAMBWIDR_EL1.HAS_HW_SCALE == 1:

Enables hardware bandwidth scaling of the MPAMBW3_EL3.MAX value.

HW_SCALE_ENABLE	Meaning
0b0	PE-side memory bandwidth control hardware scaling in EL3 is disabled.
0b1	PE-side memory bandwidth control hardware scaling in EL3 is enabled.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

ENABLED, bit [62]

Enables the PE-side memory bandwidth control when in EL3.

ENABLED	Meaning
0b0	The PE-side memory bandwidth control in EL3 is disabled.
0b1	The PE-side memory bandwidth control in EL3 is enabled.

The reset behavior of this field is:

On a Warm reset, when the highest implemented Exception level is EL3, this field resets to '0'.

HARDLIM, bit [61]

PE-side Maximum Bandwidth Limit Behavior Selection.

HARDLIM	Meaning
0b0	Soft limit: when MPAMBW3_EL3.MAX bandwidth is exceeded, the PE is unregulated unless the downstream memory path is saturated. It is IMPLEMENTATION DEFINED how hardware determines when the downstream memory path is saturated.
0b1	Hard limit: when MPAMBW3_EL3.MAX bandwidth is exceeded, the PE does not use any more bandwidth until the memory bandwidth for the PE falls below MPAMBW3_EL3.MAX.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing this field has the following behavior:

When MPAMBWIDR_EL1.MAX_LIM == 0b00, access to this field is RW.
When MPAMBWIDR_EL1.MAX_LIM == 0b01, access to this field is RAZ/WI.
When MPAMBWIDR_EL1.MAX_LIM == 0b10, access to this field is RAO/WI.

Bits [60:50]

nTRAPLOWER, bit [49]

Traps accesses to MPAMBW2_EL2, MPAMBWCAP_EL2, MPAMBW1_EL1, MPAMBW0_EL1, MPAMBWSM_EL1, MPAMBWIDR_EL1 from any lower EL to EL3.

nTRAPLOWER	Meaning
0b0	Accesses to MPAMBW2_EL2, MPAMBWCAP_EL2, MPAMBW1_EL1, MPAMBW0_EL1, MPAMBWSM_EL1, MPAMBWIDR_EL1 from EL1 are trapped to EL3 with EC syndrome value 0x18.
0b1	Accesses to MPAMBW2_EL2, MPAMBWCAP_EL2, MPAMBW1_EL1, MPAMBW0_EL1, MPAMBWSM_EL1, MPAMBWIDR_EL1 from EL1 are not trapped by this mechanism.

Note

This trap is higher priority than any of the traps controlled by MPAM _EL2 registers.

The reset behavior of this field is:

On a Warm reset, when the highest implemented Exception level is EL3, this field resets to '0'.

Bits [48:32]

MAX, bits [31:0]

MAX encoding when MPAMBWIDR_EL1.HAS_HW_SCALE == 1 and MPAMBW3_EL3.HW_SCALE_ENABLE == 1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MAX

MAX, bits [31:0]

Maximum memory bandwidth allocated to the PE when executing at EL3 with its current PARTID.

The value is represented as a multiplier of the available bandwidth for the PE. The value is represented in base-2 fixed-point format.

Bits [31:16] represent the integer part of the value.

Bits [15:(16 - MPAMBWIDR_EL1.BWA_WD)] represent the fractional part of the value. When MPAMBWIDR_EL1.BWA_WD indicates a width less than 16 bits, bits [(15 - MPAMBWIDR_EL1.BWA_WD):0] are RES0.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

MAX encoding when MPAMBWIDR_EL1.HAS_HW_SCALE == 0 or MPAMBW3_EL3.HW_SCALE_ENABLE == 0

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																MAX

Bits [31:16]

Reserved, RES0.

MAX, bits [15:0]

Maximum memory bandwidth allocated to the PE when executing at EL3 with its current PARTID.

The value is represented as a fraction of the available bandwidth for the PE. The value is represented in base-2 fixed-point format.

Bits [15:(16 - MPAMBWIDR_EL1.BWA_WD)] represent the fractional part of the value. When MPAMBWIDR_EL1.BWA_WD indicates a width less than 16 bits, bits [(15 - MPAMBWIDR_EL1.BWA_WD):0] are RES0.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing MPAMBW3_EL3

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, MPAMBW3_EL3

op0	op1	CRn	CRm	op2
0b11	0b110	0b1010	0b0101	0b100

if !IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then X[t, 64] = MPAMBW3_EL3;

MSR MPAMBW3_EL3, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b110	0b1010	0b0101	0b100

MPAMBW3_EL3, MPAM PE-side Maximum-bandwidth Control Register (EL3)

Purpose

Configuration

Attributes

Field descriptions

HW_SCALE_ENABLE, bit [63]
When MPAMBWIDR_EL1.HAS_HW_SCALE == 1:

Otherwise:

ENABLED, bit [62]

HARDLIM, bit [61]

Bits [60:50]

nTRAPLOWER, bit [49]

Bits [48:32]

MAX, bits [31:0]

MAX encoding when MPAMBWIDR_EL1.HAS_HW_SCALE == 1 and MPAMBW3_EL3.HW_SCALE_ENABLE == 1

MAX, bits [31:0]

MAX encoding when MPAMBWIDR_EL1.HAS_HW_SCALE == 0 or MPAMBW3_EL3.HW_SCALE_ENABLE == 0

Bits [31:16]

MAX, bits [15:0]

Accessing MPAMBW3_EL3

MRS <Xt>, MPAMBW3_EL3

MSR MPAMBW3_EL3, <Xt>

MPAMBW3_EL3, MPAM PE-side Maximum-bandwidth Control Register (EL3)

Purpose

Configuration

Attributes

Field descriptions

HW_SCALE_ENABLE, bit [63]When MPAMBWIDR_EL1.HAS_HW_SCALE == 1:

Otherwise:

ENABLED, bit [62]

HARDLIM, bit [61]

Bits [60:50]

nTRAPLOWER, bit [49]

Bits [48:32]

MAX, bits [31:0]

MAX encoding when MPAMBWIDR_EL1.HAS_HW_SCALE == 1 and MPAMBW3_EL3.HW_SCALE_ENABLE == 1

MAX, bits [31:0]

MAX encoding when MPAMBWIDR_EL1.HAS_HW_SCALE == 0 or MPAMBW3_EL3.HW_SCALE_ENABLE == 0

Bits [31:16]

MAX, bits [15:0]

Accessing MPAMBW3_EL3

MRS <Xt>, MPAMBW3_EL3

MSR MPAMBW3_EL3, <Xt>

HW_SCALE_ENABLE, bit [63]
When MPAMBWIDR_EL1.HAS_HW_SCALE == 1: