The MPAMBWIDR_EL1 characteristics are:
Indicates the supported PE-side memory bandwidth parameter values.
This register is present only when FEAT_MPAM_PE_BW_CTRL is implemented. Otherwise, direct accesses to MPAMBWIDR_EL1 are UNDEFINED.
MPAMBWIDR_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HAS_HW_SCALE | RES0 | ||||||||||||||||||||||||||||||
| MAX_LIM | RES0 | BWA_WD | |||||||||||||||||||||||||||||
Indicates whether hardware support for auto-scaling of MPAMBWn_ELx.MAX, MPAMBWSM_EL1.MAX and MPAMBWCAP_EL2.CAP limits is available.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| HAS_HW_SCALE | Meaning |
|---|---|
| 0b0 |
Hardware support for auto-scaling is not implemented. |
| 0b1 |
Hardware support for auto-scaling is implemented. |
Access to this field is RO.
Reserved, RES0.
Indicates the implemented maximum-bandwidth limit partitioning behaviors.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| MAX_LIM | Meaning |
|---|---|
| 0b00 |
Both soft limit and hard limit behaviors are implemented. |
| 0b01 |
Soft limit behavior is implemented. |
| 0b10 |
Hard limit behavior is implemented. |
| 0b11 |
Reserved. |
Access to this field is RO.
Reserved, RES0.
Indicates the number of implemented bits in the bandwidth allocation fields MPAMBWn_ELx.MAX, MPAMBWSM_EL1.MAX and MPAMBWCAP_EL2.CAP.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| BWA_WD | Meaning |
|---|---|
| 0b000001..0b010000 |
Number of implemented bits in the bandwidth allocation fields. |
Access to this field is RO.
Accesses to this register use the following encodings in the System register encoding space:
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1010 | 0b0100 | 0b101 |
if !IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MPAM3_EL3.TRAPLOWER == '1' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && MPAMBW3_EL3.nTRAPLOWER == '0' then UNDEFINED; elsif HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MPAMBW3_EL3.nTRAPLOWER == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && MPAMBW2_EL2.nTRAP_MPAMBWIDR_EL1 == '0' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = MPAMBWIDR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MPAM3_EL3.TRAPLOWER == '1' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && MPAMBW3_EL3.nTRAPLOWER == '0' then UNDEFINED; elsif HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MPAMBW3_EL3.nTRAPLOWER == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = MPAMBWIDR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = MPAMBWIDR_EL1;
15/12/2024 22:27; 5e0a212688c6bd7aee92394b6f5e491b4d0fee1d
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