The MPAMBW2_EL2 characteristics are:
Enables software to configure a maximum fraction of memory bandwidth that the PE is permitted to use when executing at EL2 with its current PARTID.
This register is present only when FEAT_MPAM_PE_BW_CTRL is implemented. Otherwise, direct accesses to MPAMBW2_EL2 are UNDEFINED.
This register has no effect if EL2 is not enabled in the current Security state.
MPAMBW2_EL2 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HW_SCALE_ENABLE | ENABLED | HARDLIM | RES0 | nTRAP_MPAMBWIDR_EL1 | nTRAP_MPAMBW0_EL1 | nTRAP_MPAMBW1_EL1 | nTRAP_MPAMBWSM_EL1 | RES0 | |||||||||||||||||||||||
| MAX | |||||||||||||||||||||||||||||||
Enables hardware bandwidth scaling of the MPAMBW2_EL2.MAX value.
| HW_SCALE_ENABLE | Meaning |
|---|---|
| 0b0 |
PE-side memory bandwidth control hardware scaling in EL2 is disabled. |
| 0b1 |
PE-side memory bandwidth control hardware scaling in EL2 is enabled. |
The reset behavior of this field is:
Reserved, RES0.
Enables the PE-side memory bandwidth control when in EL2.
| ENABLED | Meaning |
|---|---|
| 0b0 |
The PE-side memory bandwidth control in EL2 is disabled. |
| 0b1 |
The PE-side memory bandwidth control in EL2 is enabled. |
The reset behavior of this field is:
PE-side Maximum Bandwidth Limit Behavior Selection.
| HARDLIM | Meaning |
|---|---|
| 0b0 |
Soft limit: when MPAMBW2_EL2.MAX bandwidth is exceeded, the PE is unregulated unless the downstream memory path is saturated. It is IMPLEMENTATION DEFINED how hardware determines when the downstream memory path is saturated. |
| 0b1 |
Hard limit: when MPAMBW2_EL2.MAX bandwidth is exceeded, the PE does not use any more bandwidth until the memory bandwidth for the PE falls below MPAMBW2_EL2.MAX. |
The reset behavior of this field is:
Accessing this field has the following behavior:
Reserved, RES0.
Traps accesses to MPAMBWIDR_EL1 from EL1 to EL2.
| nTRAP_MPAMBWIDR_EL1 | Meaning |
|---|---|
| 0b0 |
Accesses to MPAMBWIDR_EL1 from EL1 are trapped to EL2 with EC syndrome value 0x18. |
| 0b1 |
Accesses to MPAMBWIDR_EL1 from EL1 are not trapped by this mechanism. |
The reset behavior of this field is:
Traps accesses to MPAMBW0_EL1 from EL1 to EL2.
| nTRAP_MPAMBW0_EL1 | Meaning |
|---|---|
| 0b0 |
Accesses to MPAMBW0_EL1 from EL1 are trapped to EL2 with EC syndrome value 0x18. |
| 0b1 |
Accesses to MPAMBW0_EL1 from EL1 are not trapped by this mechanism. |
The reset behavior of this field is:
Traps accesses to MPAMBW1_EL1 from EL1 to EL2.
| nTRAP_MPAMBW1_EL1 | Meaning |
|---|---|
| 0b0 |
Accesses to MPAMBW1_EL1 from EL1 are trapped to EL2 with EC syndrome value 0x18. |
| 0b1 |
Accesses to MPAMBW1_EL1 from EL1 are not trapped by this mechanism. |
The reset behavior of this field is:
Traps accesses to MPAMBWSM_EL1 from EL1 to EL2.
| nTRAP_MPAMBWSM_EL1 | Meaning |
|---|---|
| 0b0 |
Accesses to MPAMBWSM_EL1 from EL1 are trapped to EL2 with EC syndrome value 0x18. |
| 0b1 |
Accesses to MPAMBWSM_EL1 from EL1 are not trapped by this mechanism. |
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MAX | |||||||||||||||||||||||||||||||
Maximum memory bandwidth allocated to the PE when executing at EL2 with its current PARTID.
The value is represented as a multiplier of the available bandwidth for the PE. The value is represented in base-2 fixed-point format.
Bits [31:16] represent the integer part of the value.
Bits [15:(16 - MPAMBWIDR_EL1.BWA_WD)] represent the fractional part of the value. When MPAMBWIDR_EL1.BWA_WD indicates a width less than 16 bits, bits [(15 - MPAMBWIDR_EL1.BWA_WD):0] are RES0.
The reset behavior of this field is:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | MAX | ||||||||||||||||||||||||||||||
Reserved, RES0.
Maximum memory bandwidth allocated to the PE when executing at EL2 with its current PARTID.
The value is represented as a fraction of the available bandwidth for the PE. The value is represented in base-2 fixed-point format.
Bits [15:(16 - MPAMBWIDR_EL1.BWA_WD)] represent the fractional part of the value. When MPAMBWIDR_EL1.BWA_WD indicates a width less than 16 bits, bits [(15 - MPAMBWIDR_EL1.BWA_WD):0] are RES0.
The reset behavior of this field is:
When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL2 using the accessor name MPAMBW2_EL2 or MPAMBW1_EL1 are not guaranteed to be ordered with respect to accesses using the other accessor name.
Accesses to this register use the following encodings in the System register encoding space:
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b100 | 0b1010 | 0b0101 | 0b100 |
if !IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MPAMBW3_EL3.nTRAPLOWER == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MPAM3_EL3.TRAPLOWER == '1' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && MPAMBW3_EL3.nTRAPLOWER == '0' then UNDEFINED; elsif HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MPAMBW3_EL3.nTRAPLOWER == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = MPAMBW2_EL2; elsif PSTATE.EL == EL3 then X[t, 64] = MPAMBW2_EL2;
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b100 | 0b1010 | 0b0101 | 0b100 |
if !IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MPAMBW3_EL3.nTRAPLOWER == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MPAM3_EL3.TRAPLOWER == '1' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && MPAMBW3_EL3.nTRAPLOWER == '0' then UNDEFINED; elsif HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MPAMBW3_EL3.nTRAPLOWER == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else MPAMBW2_EL2 = X[t, 64]; elsif PSTATE.EL == EL3 then MPAMBW2_EL2 = X[t, 64];
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1010 | 0b0101 | 0b100 |
if !IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MPAM3_EL3.TRAPLOWER == '1' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && MPAMBW3_EL3.nTRAPLOWER == '0' then UNDEFINED; elsif HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MPAMBW3_EL3.nTRAPLOWER == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && MPAMBW2_EL2.nTRAP_MPAMBW1_EL1 == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then X[t, 64] = NVMem[0x908]; else X[t, 64] = MPAMBW1_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MPAM3_EL3.TRAPLOWER == '1' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && MPAMBW3_EL3.nTRAPLOWER == '0' then UNDEFINED; elsif HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MPAMBW3_EL3.nTRAPLOWER == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif ELIsInHost(EL2) then X[t, 64] = MPAMBW2_EL2; else X[t, 64] = MPAMBW1_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = MPAMBW1_EL1;
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1010 | 0b0101 | 0b100 |
if !IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MPAM3_EL3.TRAPLOWER == '1' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && MPAMBW3_EL3.nTRAPLOWER == '0' then UNDEFINED; elsif HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MPAMBW3_EL3.nTRAPLOWER == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && MPAMBW2_EL2.nTRAP_MPAMBW1_EL1 == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem[0x908] = X[t, 64]; else MPAMBW1_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MPAM3_EL3.TRAPLOWER == '1' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && MPAMBW3_EL3.nTRAPLOWER == '0' then UNDEFINED; elsif HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MPAMBW3_EL3.nTRAPLOWER == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif ELIsInHost(EL2) then MPAMBW2_EL2 = X[t, 64]; else MPAMBW1_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then MPAMBW1_EL1 = X[t, 64];
15/12/2024 22:27; 5e0a212688c6bd7aee92394b6f5e491b4d0fee1d
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