The PMSCR_EL1 characteristics are:
Provides EL1 controls for Statistical Profiling.
This register is present only when FEAT_SPE is implemented. Otherwise, direct accesses to PMSCR_EL1 are UNDEFINED.
PMSCR_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | EnVM | KE | EE | PCT | TS | PA | CX | RES0 | E1SPE | E0SPE | |||||||||||||||||||||
Reserved, RES0.
Reserved for software use in nested virtualization. See also PMSCR_EL2.EnVM.
The reset behavior of this field is:
Reserved, RES0.
Kernel exception enable for SPE Profiling exceptions taken to EL1.
| KE | Meaning |
|---|---|
| 0b0 |
SPE Profiling exceptions taken to EL1 are always masked at EL1. |
| 0b1 |
Enabled SPE Profiling exceptions taken to EL1 are masked at EL1 when PSTATE.PM is 1 and unmasked when PSTATE.PM is 0. |
The reset behavior of this field is:
Reserved, RES0.
Exception Enable.
| EE | Meaning | Applies when |
|---|---|---|
| 0b00 | Disabled. SPE Profiling exceptions for EL1 are disabled. All of the following apply: | |
| 0b01 |
Reserved for software use in nested virtualization. Behaves as 0b00 for the purpose of controlling the SPE Profiling exception and interrupt request signal PMBIRQ, and as 0b11 for the purpose of accesses to PMBSR_EL1. | When FEAT_NV is implemented |
| 0b10 |
Reserved for software use in nested virtualization. Behaves as 0b11 for the purposes of controlling the SPE Profiling exception and interrupt request signal PMBIRQ, and accesses to PMBSR_EL1. | When FEAT_NV is implemented |
| 0b11 | Enabled. SPE Profiling exceptions for EL1 are enabled, as follows:
|
For more information on the values reserved for software use in nested virtualization, see PMSCR_EL2.EE.
If the Effective value of PMSCR_EL2.EE is 0b00, then the Effective value of PMSCR_EL1.EE is 0b00.
The reset behavior of this field is:
Reserved, RES0.
Physical Timestamp. If timestamp sampling is enabled and the Profiling Buffer is owned by EL1, requests which timestamp counter value is collected.
If FEAT_ECV is implemented, this is a two-bit field as shown. Otherwise, bit[7] is RES0.
| PCT | Meaning | Applies when |
|---|---|---|
| 0b00 |
Virtual timestamp. The collected timestamp is the physical counter minus the value of CNTVOFF_EL2. | |
| 0b01 |
Physical timestamp. The collected timestamp is the physical counter. | |
| 0b11 | Guest physical timestamp. The collected timestamp is the physical counter minus a physical offset. If any of the following are true, the physical offset is zero, otherwise the physical offset is the value of CNTPOFF_EL2:
| When FEAT_ECV is implemented |
If EL2 is enabled in the current Security state, then the value of PMSCR_EL2.PCT might override or modify the meaning of this field.
This field is ignored by the PE when the Profiling Buffer owning Exception level is EL2.
The reset behavior of this field is:
Physical Timestamp. Reserved. This field reads as 0b01 and ignores writes. Software should treat this field as UNK/SBZP.
When EL2 is not implemented, the Effective values of CNTVOFF_EL2 and CNTPOFF_EL2 are zero, meaning the virtual counter and physical counter have the same value.
Timestamp enable.
| TS | Meaning |
|---|---|
| 0b0 |
Timestamp sampling disabled. |
| 0b1 |
Timestamp sampling enabled. |
This bit is ignored by the PE if EL2 is implemented and the Profiling Buffer is owned by EL2. For more information, see 'Controlling the data that is collected'.
The reset behavior of this field is:
Physical Address sample enable.
| PA | Meaning |
|---|---|
| 0b0 |
Physical addresses are not collected. |
| 0b1 |
Physical addresses are collected. |
If EL2 is implemented:
The reset behavior of this field is:
CONTEXTIDR_EL1 sample enable.
| CX | Meaning |
|---|---|
| 0b0 |
CONTEXTIDR_EL1 is not collected. |
| 0b1 |
CONTEXTIDR_EL1 is collected. |
If EL2 is implemented and enabled in the current Security state when an operation is sampled:
The reset behavior of this field is:
Reserved, RES0.
EL1 Statistical Profiling Enable.
| E1SPE | Meaning |
|---|---|
| 0b0 |
Sampling disabled at EL1. |
| 0b1 |
Sampling enabled at EL1. |
If EL2 is implemented and enabled in the current Security state, this bit is ignored by the PE when HCR_EL2.TGE == 1.
The reset behavior of this field is:
EL0 Statistical Profiling Enable. Controls sampling at EL0 when HCR_EL2.TGE == 0 or if EL2 is disabled or not implemented.
| E0SPE | Meaning |
|---|---|
| 0b0 |
Sampling disabled at EL0. |
| 0b1 |
Sampling enabled at EL0. |
If EL2 is implemented and enabled in the current Security state, this bit is ignored by the PE when HCR_EL2.TGE == 1.
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1001 | 0b1001 | 0b000 |
if !IsFeatureImplemented(FEAT_SPE) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMSCR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPMS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then X[t, 64] = NVMem[0x828]; else X[t, 64] = PMSCR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif ELIsInHost(EL2) then X[t, 64] = PMSCR_EL2; else X[t, 64] = PMSCR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = PMSCR_EL1;
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1001 | 0b1001 | 0b000 |
if !IsFeatureImplemented(FEAT_SPE) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.PMSCR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPMS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem[0x828] = X[t, 64]; else PMSCR_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif ELIsInHost(EL2) then PMSCR_EL2 = X[t, 64]; else PMSCR_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then PMSCR_EL1 = X[t, 64];
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b101 | 0b1001 | 0b1001 | 0b000 |
if !IsFeatureImplemented(FEAT_SPE) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X[t, 64] = NVMem[0x828]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMSCR_EL1; else UNDEFINED; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X[t, 64] = PMSCR_EL1; else UNDEFINED;
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b101 | 0b1001 | 0b1001 | 0b000 |
if !IsFeatureImplemented(FEAT_SPE) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem[0x828] = X[t, 64]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMSCR_EL1 = X[t, 64]; else UNDEFINED; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then PMSCR_EL1 = X[t, 64]; else UNDEFINED;
15/12/2024 22:27; 5e0a212688c6bd7aee92394b6f5e491b4d0fee1d
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