The PMBSR_EL2 characteristics are:
Provides syndrome information to software for a Profiling Buffer management event.
This register is present only when FEAT_SPE_EXC is implemented. Otherwise, direct accesses to PMBSR_EL2 are UNDEFINED.
If EL2 is not implemented, this register is RES0 from EL3.
PMBSR_EL2 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | MSS2 | ||||||||||||||||||||||||||||||
EC | RES0 | DL | EA | S | COLL | MSS |
Reserved, RES0.
Management event Specific Syndrome 2. Contains syndrome specific to the management event.
The syndrome contents for each management event are described in the following sections.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 |
Reserved, RES0.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | TopLevel | AssuredOnly | Overlay | DirtyBit | RES0 |
Reserved, RES0.
TopLevel. Indicates if the fault was due to TopLevel.
TopLevel | Meaning |
---|---|
0b0 |
Fault is not due to TopLevel. |
0b1 |
Fault is due to TopLevel. |
Reserved, RES0.
AssuredOnly flag. If a memory access generates a stage 2 Data Abort, then this field holds information about the fault.
AssuredOnly | Meaning |
---|---|
0b0 |
Data Abort is not due to AssuredOnly. |
0b1 |
Data Abort is due to AssuredOnly. |
Reserved, RES0.
Overlay flag. If a memory access generates a Data Abort for a Permission fault, then this field holds information about the fault.
Overlay | Meaning |
---|---|
0b0 |
Data Abort is not due to Overlay Permissions. |
0b1 |
Data Abort is due to Overlay Permissions. |
Reserved, RES0.
DirtyBit flag. If a write access to memory generates a Data Abort for a Permission fault using Indirect Permission, then this field holds information about the fault.
DirtyBit | Meaning |
---|---|
0b0 |
Permission Fault is not due to dirty state. |
0b1 |
Permission Fault is due to dirty state. |
Reserved, RES0.
Reserved, RES0.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 |
Reserved, RES0.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED |
IMPLEMENTATION DEFINED.
Event class. Top-level description of the cause of the Profiling Buffer management event.
EC | Meaning | MSS | MSS2 | Applies when |
---|---|---|---|---|
0b000000 |
Other Profiling Buffer management event. All Profiling Buffer management events other than those described by the other defined Event class codes. | MSS encoding for other Profiling Buffer management events | MSS2 encoding for other Profiling Buffer management events | |
0b011110 | Granule Protection Check fault on write to Profiling Buffer, other than Granule Protection Fault (GPF). That is, any of the following:
A GPF on translation table walk or update is reported as either a Stage 1 or Stage 2 Data Abort, as appropriate. Other GPFs are reported as a Stage 1 Data Abort. | MSS encoding for Granule Protection Check faults on write to Profiling Buffer | MSS2 encoding for Granule Protection Check faults on write to Profiling Buffer | When FEAT_RME is implemented |
0b011111 |
Profiling Buffer management event for an IMPLEMENTATION DEFINED reason. | MSS encoding for Profiling Buffer management event for an IMPLEMENTATION DEFINED reason | MSS2 encoding for Profiling Buffer management event for an IMPLEMENTATION DEFINED reason | |
0b100100 |
Stage 1 Data Abort on write to Profiling Buffer. | MSS encoding for stage 1 or stage 2 Data Aborts on write to Profiling Buffer | MSS2 encoding for stage 1 or stage 2 Data Aborts on write to Profiling Buffer | |
0b100101 |
Stage 2 Data Abort on write to Profiling Buffer. | MSS encoding for stage 1 or stage 2 Data Aborts on write to Profiling Buffer | MSS2 encoding for stage 1 or stage 2 Data Aborts on write to Profiling Buffer |
All other values are reserved.
The reset behavior of this field is:
Reserved, RES0.
Partial record lost. Following a buffer management event other than an asynchronous External abort, indicates whether the last record written to the Profiling Buffer is complete.
DL | Meaning |
---|---|
0b0 |
PMBPTR_EL1 points to the first byte after the last complete record written to the Profiling Buffer. |
0b1 |
Part of a record was lost because of a buffer management event or synchronous External abort. PMBPTR_EL1 might not point to the first byte after the last complete record written to the buffer, and so restarting collection might result in a data record stream that software cannot parse. |
When the buffer management event was because of an asynchronous External abort, this bit is set to 1 and software must not assume that any valid data has been written to the Profiling Buffer.
This bit is RES0 if the PE never sets this bit as a result of a buffer management event caused by an asynchronous External abort.
The reset behavior of this field is:
External abort.
EA | Meaning |
---|---|
0b0 |
An External abort has not been asserted. |
0b1 |
An External abort has been asserted and detected by the Statistical Profiling Unit. |
This bit is RES0 if the PE never sets this bit as the result of an External abort.
The reset behavior of this field is:
Service. Indicates that a Profiling Buffer management event has been recorded.
S | Meaning |
---|---|
0b0 |
No Profiling Buffer management event for EL2 has been recorded. |
0b1 |
A Profiling Buffer management event for EL2 has been recorded. |
When FEAT_SPE_EXC is implemented, this field indicates a management event for EL2.
If the SPE Profiling exception for EL2 is enabled, then when this field is 1, an SPE Profiling exception for EL2 is pending
The reset behavior of this field is:
Collision detected.
COLL | Meaning |
---|---|
0b0 |
No collision events detected. |
0b1 |
At least one collision event was recorded. |
The reset behavior of this field is:
Management Event Specific Syndrome. Contains syndrome specific to the Profiling Buffer management event.
The syndrome contents for each Profiling Buffer management event are described in the following sections.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | BSC |
Reserved, RES0.
Profiling Buffer status code
BSC | Meaning |
---|---|
0b000000 |
Collection not stopped, or access not allowed. |
0b000001 |
Profiling Buffer filled. |
0b000100 |
Buffer size. The requested Profiling Buffer size was too large. |
All other values are reserved.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | FSC |
Reserved, RES0.
Fault status code
FSC | Meaning | Applies when |
---|---|---|
0b000000 |
Address size fault, level 0 of translation or translation table base register. | |
0b000001 |
Address size fault, level 1. | |
0b000010 |
Address size fault, level 2. | |
0b000011 |
Address size fault, level 3. | |
0b000100 |
Translation fault, level 0. | |
0b000101 |
Translation fault, level 1. | |
0b000110 |
Translation fault, level 2. | |
0b000111 |
Translation fault, level 3. | |
0b001001 |
Access flag fault, level 1. | |
0b001010 |
Access flag fault, level 2. | |
0b001011 |
Access flag fault, level 3. | |
0b001000 |
Access flag fault, level 0. | When FEAT_LPA2 is implemented |
0b001100 |
Permission fault, level 0. | When FEAT_LPA2 is implemented |
0b001101 |
Permission fault, level 1. | |
0b001110 |
Permission fault, level 2. | |
0b001111 |
Permission fault, level 3. | |
0b010000 |
Synchronous External abort, not on translation table walk or hardware update of translation table. | |
0b010001 |
Asynchronous External abort. | |
0b010010 |
Synchronous External abort on translation table walk or hardware update of translation table, level -2. | When FEAT_D128 is implemented |
0b010011 |
Synchronous External abort on translation table walk or hardware update of translation table, level -1. | When FEAT_LPA2 is implemented |
0b010100 |
Synchronous External abort on translation table walk or hardware update of translation table, level 0. | |
0b010101 |
Synchronous External abort on translation table walk or hardware update of translation table, level 1. | |
0b010110 |
Synchronous External abort on translation table walk or hardware update of translation table, level 2. | |
0b010111 |
Synchronous External abort on translation table walk or hardware update of translation table, level 3. | |
0b011011 |
Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level -1. | When FEAT_LPA2 is implemented and FEAT_RAS is not implemented |
0b100001 |
Alignment fault. | |
0b100010 |
Granule Protection Fault on translation table walk or hardware update of translation table, level -2. | When FEAT_D128 is implemented and FEAT_RME is implemented |
0b100011 |
Granule Protection Fault on translation table walk or hardware update of translation table, level -1. | When FEAT_RME is implemented and FEAT_LPA2 is implemented |
0b100100 |
Granule Protection Fault on translation table walk or hardware update of translation table, level 0. | When FEAT_RME is implemented |
0b100101 |
Granule Protection Fault on translation table walk or hardware update of translation table, level 1. | When FEAT_RME is implemented |
0b100110 |
Granule Protection Fault on translation table walk or hardware update of translation table, level 2. | When FEAT_RME is implemented |
0b100111 |
Granule Protection Fault on translation table walk or hardware update of translation table, level 3. | When FEAT_RME is implemented |
0b101000 |
Granule Protection Fault, not on translation table walk or hardware update of translation table. | When FEAT_RME is implemented |
0b101001 |
Address size fault, level -1. | When FEAT_LPA2 is implemented |
0b101010 |
Translation fault, level -2. | When FEAT_D128 is implemented |
0b101011 |
Translation fault, level -1. | When FEAT_LPA2 is implemented |
0b101100 |
Address Size fault, level -2. | When FEAT_D128 is implemented |
0b110000 |
TLB conflict abort. | |
0b110001 |
Unsupported atomic hardware update fault. | When FEAT_HAFDBS is implemented |
All other values are reserved.
It is IMPLEMENTATION DEFINED whether each of the Access Flag fault, asynchronous External abort and synchronous External abort, Alignment fault, and TLB Conflict abort values can be generated by the PE. For more information see 'Faults and Watchpoints'.
The reset behavior of this field is:
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 |
Reserved, RES0.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED |
IMPLEMENTATION DEFINED.
When the Effective value of HCR_EL2.E2H is 1 and FEAT_SPE_EXC is implemented, without explicit synchronization, accesses from EL2 using the accessor name PMBSR_EL2 or PMBSR_EL1 are not guaranteed to be ordered with respect to accesses using the other accessor name.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b1001 | 0b1010 | 0b011 |
if !IsFeatureImplemented(FEAT_SPE_EXC) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.PMSEE == '00' then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.PMSEE == '00' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMBSR_EL2; elsif PSTATE.EL == EL3 then X[t, 64] = PMBSR_EL2;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b1001 | 0b1010 | 0b011 |
if !IsFeatureImplemented(FEAT_SPE_EXC) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.PMSEE == '00' then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.PMSEE == '00' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMBSR_EL2 = X[t, 64]; elsif PSTATE.EL == EL3 then PMBSR_EL2 = X[t, 64];
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1001 | 0b1010 | 0b011 |
if !IsFeatureImplemented(FEAT_SPE) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMBSR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.E2PB IN {'x0'} then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'1x1'} && (EffectivePMSCR_EL2_EE() == '00' || PMSCR_EL1.EE == '00' || EffectiveHCR_EL2_NVx() == '111') then X[t, 64] = NVMem[0x820]; else X[t, 64] = PMBSR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectivePMSCR_EL2_EE() != '00' && ELIsInHost(EL2) then X[t, 64] = PMBSR_EL2; else X[t, 64] = PMBSR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = PMBSR_EL1;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1001 | 0b1010 | 0b011 |
if !IsFeatureImplemented(FEAT_SPE) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.PMBSR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.E2PB IN {'x0'} then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'1x1'} && (EffectivePMSCR_EL2_EE() == '00' || PMSCR_EL1.EE == '00' || EffectiveHCR_EL2_NVx() == '111') then NVMem[0x820] = X[t, 64]; else PMBSR_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectivePMSCR_EL2_EE() != '00' && ELIsInHost(EL2) then PMBSR_EL2 = X[t, 64]; else PMBSR_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then PMBSR_EL1 = X[t, 64];
15/12/2024 22:27; 5e0a212688c6bd7aee92394b6f5e491b4d0fee1d
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.