TRFCR_EL1

AArch64 System register TRFCR_EL1 bits [31:0] are architecturally mapped to AArch32 System register TRFCR[31:0].

This register is present only when FEAT_TRF is implemented. Otherwise, direct accesses to TRFCR_EL1 are UNDEFINED.

Attributes

Field descriptions

Bits [63:12]

DnVM, bit [11]
When FEAT_TRBEv1p1 is implemented and FEAT_NV is implemented:

Otherwise:

KE, bit [10]
When FEAT_TRBE_EXC is implemented:

KE	Meaning
0b0	TRBE Profiling exceptions taken to EL1 are always masked at EL1.
0b1	Enabled TRBE Profiling exceptions taken to EL1 are masked at EL1 when PSTATE.PM is 1 and unmasked when PSTATE.PM is 0.

Otherwise:

EE, bits [9:8]
When FEAT_TRBE_EXC is implemented:

Exception Enable.

EE	Meaning	Applies when
0b00	Disabled. TRBE Profiling exceptions for EL1 are disabled. All of the following apply: Unless enabled by a higher Exception level, TRBE Profiling exceptions are not generated. TRBSR_EL1.IRQ drives the interrupt request signal TRBIRQ. Accesses to TRBSR_EL1 at EL1 ignore the value of HCR_EL2.NV1.
0b01	Reserved for software use in nested virtualization. Behaves as 0b00 for the purpose of controlling the TRBE Profiling exception and interrupt request signal TRBIRQ, and as 0b11 for the purpose of accesses to TRBSR_EL1.	When FEAT_NV is implemented
0b10	Reserved for software use in nested virtualization. Behaves as 0b11 for the purposes of controlling the TRBE Profiling exception and interrupt request signal TRBIRQ, and accesses to TRBSR_EL1.	When FEAT_NV is implemented
0b11	Enabled. TRBE Profiling exceptions for EL1 are enabled, as follows: All trace buffer management events are recorded in TRBSR_EL1, unless they are configured to be recorded in TRBSR_EL3 by MDCR_EL3.TRBEE or TRBSR_EL2 by TRFCR_EL2.EE. TRBE Profiling exceptions are generated and taken to EL1 when unmasked and TRBSR_EL1.IRQ is 1, unless the Effective value of HCR_EL2.TGE is 1, in which case the exception is taken to EL2. The interrupt request signal TRBIRQ is not asserted.

For more information on the values reserved for software use in nested virtualization, see TRFCR_EL2.EE.

If the Effective value of TRFCR_EL2.EE is 0b00, then the Effective value of TRFCR_EL1.EE is 0b00.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL1, this field resets to '00'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bit [7]

TS, bits [6:5]

Timestamp Control. Controls which timebase is used for trace timestamps.

TS	Meaning	Applies when
0b00	Reserved for software use in nested virtualization. Behaves as 0b01. See also TRFCR_EL2.TS,	When FEAT_NV2p1 is implemented
0b01	Virtual timestamp. The traced timestamp is the physical counter value minus the value of CNTVOFF_EL2.
0b10	Guest physical timestamp. The traced timestamp is the physical counter value minus a physical offset. If any of the following are true, the physical offset is zero, otherwise the physical offset is the value of CNTPOFF_EL2: SCR_EL3.ECVEn == 0. CNTHCTL_EL2.ECV == 0. FEAT_ECV_POFF is not implemented.	When FEAT_ECV is implemented
0b11	Physical timestamp. The traced timestamp is the physical counter value.

All other values are reserved.

This field is ignored by the PE when any of the following are true:

EL2 is implemented and TRFCR_EL2.TS != 0b00.
SelfHostedTraceEnabled() == FALSE.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bit [4]

CX, bit [3]
When FEAT_NV2p1 is implemented:

Otherwise:

Bit [2]

E1TRE, bit [1]

E0TRE, bit [0]

E1TRE	Meaning
0b0	Trace is prohibited at EL1.
0b1	Trace is allowed at EL1.

E0TRE	Meaning
0b0	Trace is prohibited at EL0.
0b1	Trace is allowed at EL0.

Accessing TRFCR_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, TRFCR_EL1

op0	op1	CRn	CRm	op2
0b11	0b000	0b0001	0b0010	0b001

if !IsFeatureImplemented(FEAT_TRF) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TTRF == '1' then UNDEFINED; elsif EL2Enabled() && MDCR_EL2.TTRF == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TTRF == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then X[t, 64] = NVMem[0x880]; else X[t, 64] = TRFCR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TTRF == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TTRF == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif ELIsInHost(EL2) then X[t, 64] = TRFCR_EL2; else X[t, 64] = TRFCR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = TRFCR_EL1;

MSR TRFCR_EL1, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b000	0b0001	0b0010	0b001

if !IsFeatureImplemented(FEAT_TRF) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TTRF == '1' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.TRFCR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TTRF == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TTRF == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem[0x880] = X[t, 64]; else TRFCR_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TTRF == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TTRF == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif ELIsInHost(EL2) then TRFCR_EL2 = X[t, 64]; else TRFCR_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then TRFCR_EL1 = X[t, 64];

MRS <Xt>, TRFCR_EL12

op0	op1	CRn	CRm	op2
0b11	0b101	0b0001	0b0010	0b001

if !IsFeatureImplemented(FEAT_TRF) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X[t, 64] = NVMem[0x880]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TTRF == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TTRF == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = TRFCR_EL1; else UNDEFINED; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X[t, 64] = TRFCR_EL1; else UNDEFINED;

MSR TRFCR_EL12, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b101	0b0001	0b0010	0b001

if !IsFeatureImplemented(FEAT_TRF) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem[0x880] = X[t, 64]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TTRF == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TTRF == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else TRFCR_EL1 = X[t, 64]; else UNDEFINED; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then TRFCR_EL1 = X[t, 64]; else UNDEFINED;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0																				DnVM	KE	EE		RES0	TS		RES0	CX	RES0	E1TRE	E0TRE

TRFCR_EL1, Trace Filter Control Register (EL1)

Purpose

Configuration

Attributes

Field descriptions

Bits [63:12]

DnVM, bit [11]
When FEAT_TRBEv1p1 is implemented and FEAT_NV is implemented:

Otherwise:

KE, bit [10]
When FEAT_TRBE_EXC is implemented:

Otherwise:

EE, bits [9:8]
When FEAT_TRBE_EXC is implemented:

Otherwise:

Bit [7]

TS, bits [6:5]

Bit [4]

CX, bit [3]
When FEAT_NV2p1 is implemented:

Otherwise:

Bit [2]

E1TRE, bit [1]

E0TRE, bit [0]

Accessing TRFCR_EL1

MRS <Xt>, TRFCR_EL1

MSR TRFCR_EL1, <Xt>

MRS <Xt>, TRFCR_EL12

MSR TRFCR_EL12, <Xt>

TRFCR_EL1, Trace Filter Control Register (EL1)

Purpose

Configuration

Attributes

Field descriptions

Bits [63:12]

DnVM, bit [11]When FEAT_TRBEv1p1 is implemented and FEAT_NV is implemented:

Otherwise:

KE, bit [10]When FEAT_TRBE_EXC is implemented:

Otherwise:

EE, bits [9:8]When FEAT_TRBE_EXC is implemented:

Otherwise:

Bit [7]

TS, bits [6:5]

Bit [4]

CX, bit [3]When FEAT_NV2p1 is implemented:

Otherwise:

Bit [2]

E1TRE, bit [1]

E0TRE, bit [0]

Accessing TRFCR_EL1

MRS <Xt>, TRFCR_EL1

MSR TRFCR_EL1, <Xt>

MRS <Xt>, TRFCR_EL12

MSR TRFCR_EL12, <Xt>

DnVM, bit [11]
When FEAT_TRBEv1p1 is implemented and FEAT_NV is implemented:

KE, bit [10]
When FEAT_TRBE_EXC is implemented:

EE, bits [9:8]
When FEAT_TRBE_EXC is implemented:

CX, bit [3]
When FEAT_NV2p1 is implemented: