FGWTE3

Provides controls for traps of MSR and MSRR writes to specified EL3 system registers.

Configuration

This register is present only when EL3 is implemented and FEAT_FGWTE3 is implemented. Otherwise, direct accesses to FGWTE3_EL3 are UNDEFINED.

Attributes

Field descriptions

MSR accesses are trapped to EL3 and reported with EC syndrome value 0x18.

MSRR accesses are trapped to EL3 and reported with EC syndrome value 0x14.

The bits in this register are sticky. Writes to these bits have the following properties:

A write of 0b0 is ignored.
A write of 0b1 updates the bit to 0b1.

Bits [63:23]

GPCBW_EL3, bit [22]
When FEAT_RME_GPC3 is implemented:

Traps accesses of GPCBW_EL3 to EL3.

GPCBW_EL3	Meaning
0b0	This control does not cause any instructions to be trapped.
0b1	MSR write accesses to the specified register are trapped to EL3 with EC syndrome value 0x18.

The reset behavior of this field is:

On a Warm reset, this field resets to '0'.

Access to this field is W1S.

Otherwise:

VBAR_EL3, bit [21]

Traps accesses of VBAR_EL3 to EL3.

VBAR_EL3	Meaning
0b0	This control does not cause any instructions to be trapped.
0b1	MSR write accesses to the specified register are trapped to EL3 with EC syndrome value 0x18.

The reset behavior of this field is:

On a Warm reset, this field resets to '0'.

Access to this field is W1S.

TTBR0_EL3, bit [20]

Traps accesses of TTBR0_EL3 to EL3.

TTBR0_EL3	Meaning
0b0	This control does not cause any instructions to be trapped.
0b1	MSR write accesses to the specified register are trapped to EL3 with EC syndrome value 0x18.

The reset behavior of this field is:

On a Warm reset, this field resets to '0'.

Access to this field is W1S.

TPIDR_EL3, bit [19]

Traps accesses of TPIDR_EL3 to EL3.

TPIDR_EL3	Meaning
0b0	This control does not cause any instructions to be trapped.
0b1	MSR write accesses to the specified register are trapped to EL3 with EC syndrome value 0x18.

The reset behavior of this field is:

On a Warm reset, this field resets to '0'.

Access to this field is W1S.

TCR_EL3, bit [18]

Traps accesses of TCR_EL3 to EL3.

TCR_EL3	Meaning
0b0	This control does not cause any instructions to be trapped.
0b1	MSR write accesses to the specified register are trapped to EL3 with EC syndrome value 0x18.

The reset behavior of this field is:

On a Warm reset, this field resets to '0'.

Access to this field is W1S.

SPMROOTCR_EL3, bit [17]
When FEAT_RME is implemented and FEAT_SPMU is implemented:

Traps accesses of SPMROOTCR_EL3 to EL3.

SPMROOTCR_EL3	Meaning
0b0	This control does not cause any instructions to be trapped.
0b1	MSR write accesses to the specified register are trapped to EL3 with EC syndrome value 0x18.

The reset behavior of this field is:

On a Warm reset, this field resets to '0'.

Access to this field is W1S.

Otherwise:

SCTLR2_EL3, bit [16]
When FEAT_SCTLR2 is implemented:

Traps accesses of SCTLR2_EL3 to EL3.

SCTLR2_EL3	Meaning
0b0	This control does not cause any instructions to be trapped.
0b1	MSR write accesses to the specified register are trapped to EL3 with EC syndrome value 0x18.

The reset behavior of this field is:

On a Warm reset, this field resets to '0'.

Access to this field is W1S.

Otherwise:

SCTLR_EL3, bit [15]

Traps accesses of SCTLR_EL3 to EL3.

SCTLR_EL3	Meaning
0b0	This control does not cause any instructions to be trapped.
0b1	MSR write accesses to the specified register are trapped to EL3 with EC syndrome value 0x18.

The reset behavior of this field is:

On a Warm reset, this field resets to '0'.

Access to this field is W1S.

PIR_EL3, bit [14]
When FEAT_S1PIE is implemented:

Traps accesses of PIR_EL3 to EL3.

PIR_EL3	Meaning
0b0	This control does not cause any instructions to be trapped.
0b1	MSR write accesses to the specified register are trapped to EL3 with EC syndrome value 0x18.

The reset behavior of this field is:

On a Warm reset, this field resets to '0'.

Access to this field is W1S.

Otherwise:

MPAM3_EL3, bit [13]
When FEAT_MPAM is implemented:

Traps accesses of MPAM3_EL3 to EL3.

MPAM3_EL3	Meaning
0b0	This control does not cause any instructions to be trapped.
0b1	MSR write accesses to the specified register are trapped to EL3 with EC syndrome value 0x18.

The reset behavior of this field is:

On a Warm reset, this field resets to '0'.

Access to this field is W1S.

Otherwise:

MECID_RL_A_EL3, bit [12]
When FEAT_MEC is implemented:

Traps accesses of MECID_RL_A_EL3 to EL3.

MECID_RL_A_EL3	Meaning
0b0	This control does not cause any instructions to be trapped.
0b1	MSR write accesses to the specified register are trapped to EL3 with EC syndrome value 0x18.

The reset behavior of this field is:

On a Warm reset, this field resets to '0'.

Access to this field is W1S.

Otherwise:

MDCR_EL3, bit [11]

Traps accesses of MDCR_EL3 to EL3.

MDCR_EL3	Meaning
0b0	This control does not cause any instructions to be trapped.
0b1	MSR write accesses to the specified register are trapped to EL3 with EC syndrome value 0x18.

The reset behavior of this field is:

On a Warm reset, this field resets to '0'.

Access to this field is W1S.

MAIR2_EL3, bit [10]
When FEAT_AIE is implemented:

Traps accesses of MAIR2_EL3 to EL3.

MAIR2_EL3	Meaning
0b0	This control does not cause any instructions to be trapped.
0b1	MSR write accesses to the specified register are trapped to EL3 with EC syndrome value 0x18.

The reset behavior of this field is:

On a Warm reset, this field resets to '0'.

Access to this field is W1S.

Otherwise:

MAIR_EL3, bit [9]

Traps accesses of MAIR_EL3 to EL3.

MAIR_EL3	Meaning
0b0	This control does not cause any instructions to be trapped.
0b1	MSR write accesses to the specified register are trapped to EL3 with EC syndrome value 0x18.

The reset behavior of this field is:

On a Warm reset, this field resets to '0'.

Access to this field is W1S.

GPTBR_EL3, bit [8]
When FEAT_RME is implemented:

Traps accesses of GPTBR_EL3 to EL3.

GPTBR_EL3	Meaning
0b0	This control does not cause any instructions to be trapped.
0b1	MSR write accesses to the specified register are trapped to EL3 with EC syndrome value 0x18.

The reset behavior of this field is:

On a Warm reset, this field resets to '0'.

Access to this field is W1S.

Otherwise:

GPCCR_EL3, bit [7]
When FEAT_RME is implemented:

Traps accesses of GPCCR_EL3 to EL3.

GPCCR_EL3	Meaning
0b0	This control does not cause any instructions to be trapped.
0b1	MSR write accesses to the specified register are trapped to EL3 with EC syndrome value 0x18.

The reset behavior of this field is:

On a Warm reset, this field resets to '0'.

Access to this field is W1S.

Otherwise:

GCSPR_EL3, bit [6]
When FEAT_GCS is implemented:

Traps accesses of GCSPR_EL3 to EL3.

GCSPR_EL3	Meaning
0b0	This control does not cause any instructions to be trapped.
0b1	MSR write accesses to the specified register are trapped to EL3 with EC syndrome value 0x18.

The reset behavior of this field is:

On a Warm reset, this field resets to '0'.

Access to this field is W1S.

Otherwise:

GCSCR_EL3, bit [5]
When FEAT_GCS is implemented:

Traps accesses of GCSCR_EL3 to EL3.

GCSCR_EL3	Meaning
0b0	This control does not cause any instructions to be trapped.
0b1	MSR write accesses to the specified register are trapped to EL3 with EC syndrome value 0x18.

The reset behavior of this field is:

On a Warm reset, this field resets to '0'.

Access to this field is W1S.

Otherwise:

AMAIR2_EL3, bit [4]
When FEAT_AIE is implemented:

Traps accesses of AMAIR2_EL3 to EL3.

AMAIR2_EL3	Meaning
0b0	This control does not cause any instructions to be trapped.
0b1	MSR write accesses to the specified register are trapped to EL3 with EC syndrome value 0x18.

The reset behavior of this field is:

On a Warm reset, this field resets to '0'.

Access to this field is W1S.

Otherwise:

AMAIR_EL3, bit [3]

Traps accesses of AMAIR_EL3 to EL3.

AMAIR_EL3	Meaning
0b0	This control does not cause any instructions to be trapped.
0b1	MSR write accesses to the specified register are trapped to EL3 with EC syndrome value 0x18.

The reset behavior of this field is:

On a Warm reset, this field resets to '0'.

Access to this field is W1S.

AFSR1_EL3, bit [2]

Traps accesses of AFSR1_EL3 to EL3.

AFSR1_EL3	Meaning
0b0	This control does not cause any instructions to be trapped.
0b1	MSR write accesses to the specified register are trapped to EL3 with EC syndrome value 0x18.

The reset behavior of this field is:

On a Warm reset, this field resets to '0'.

Access to this field is W1S.

AFSR0_EL3, bit [1]

Traps accesses of AFSR0_EL3 to EL3.

AFSR0_EL3	Meaning
0b0	This control does not cause any instructions to be trapped.
0b1	MSR write accesses to the specified register are trapped to EL3 with EC syndrome value 0x18.

The reset behavior of this field is:

On a Warm reset, this field resets to '0'.

Access to this field is W1S.

ACTLR_EL3, bit [0]

Traps accesses of ACTLR_EL3 to EL3.

ACTLR_EL3	Meaning
0b0	This control does not cause any instructions to be trapped.
0b1	MSR write accesses to the specified register are trapped to EL3 with EC syndrome value 0x18.

The reset behavior of this field is:

On a Warm reset, this field resets to '0'.

Access to this field is W1S.

Accessing FGWTE3_EL3

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, FGWTE3_EL3

op0	op1	CRn	CRm	op2
0b11	0b110	0b0001	0b0001	0b101

if !(HaveEL(EL3) && IsFeatureImplemented(FEAT_FGWTE3)) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then X[t, 64] = FGWTE3_EL3;

MSR FGWTE3_EL3, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b110	0b0001	0b0001	0b101

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0									GPCBW_EL3	VBAR_EL3	TTBR0_EL3	TPIDR_EL3	TCR_EL3	SPMROOTCR_EL3	SCTLR2_EL3	SCTLR_EL3	PIR_EL3	MPAM3_EL3	MECID_RL_A_EL3	MDCR_EL3	MAIR2_EL3	MAIR_EL3	GPTBR_EL3	GPCCR_EL3	GCSPR_EL3	GCSCR_EL3	AMAIR2_EL3	AMAIR_EL3	AFSR1_EL3	AFSR0_EL3	ACTLR_EL3

FGWTE3_EL3, Fine-Grained Write Traps EL3

Purpose

Configuration

Attributes

Field descriptions

Bits [63:23]

GPCBW_EL3, bit [22]When FEAT_RME_GPC3 is implemented:

Otherwise:

VBAR_EL3, bit [21]

TTBR0_EL3, bit [20]

TPIDR_EL3, bit [19]

TCR_EL3, bit [18]

SPMROOTCR_EL3, bit [17]When FEAT_RME is implemented and FEAT_SPMU is implemented:

Otherwise:

SCTLR2_EL3, bit [16]When FEAT_SCTLR2 is implemented:

Otherwise:

SCTLR_EL3, bit [15]

PIR_EL3, bit [14]When FEAT_S1PIE is implemented:

Otherwise:

MPAM3_EL3, bit [13]When FEAT_MPAM is implemented:

Otherwise:

MECID_RL_A_EL3, bit [12]When FEAT_MEC is implemented:

Otherwise:

MDCR_EL3, bit [11]

MAIR2_EL3, bit [10]When FEAT_AIE is implemented:

Otherwise:

MAIR_EL3, bit [9]

GPTBR_EL3, bit [8]When FEAT_RME is implemented:

Otherwise:

GPCCR_EL3, bit [7]When FEAT_RME is implemented:

Otherwise:

GCSPR_EL3, bit [6]When FEAT_GCS is implemented:

Otherwise:

GCSCR_EL3, bit [5]When FEAT_GCS is implemented:

Otherwise:

AMAIR2_EL3, bit [4]When FEAT_AIE is implemented:

Otherwise:

AMAIR_EL3, bit [3]

AFSR1_EL3, bit [2]

AFSR0_EL3, bit [1]

ACTLR_EL3, bit [0]

Accessing FGWTE3_EL3

MRS <Xt>, FGWTE3_EL3

MSR FGWTE3_EL3, <Xt>

GPCBW_EL3, bit [22]
When FEAT_RME_GPC3 is implemented:

SPMROOTCR_EL3, bit [17]
When FEAT_RME is implemented and FEAT_SPMU is implemented:

SCTLR2_EL3, bit [16]
When FEAT_SCTLR2 is implemented:

PIR_EL3, bit [14]
When FEAT_S1PIE is implemented:

MPAM3_EL3, bit [13]
When FEAT_MPAM is implemented:

MECID_RL_A_EL3, bit [12]
When FEAT_MEC is implemented:

MAIR2_EL3, bit [10]
When FEAT_AIE is implemented:

GPTBR_EL3, bit [8]
When FEAT_RME is implemented:

GPCCR_EL3, bit [7]
When FEAT_RME is implemented:

GCSPR_EL3, bit [6]
When FEAT_GCS is implemented:

GCSCR_EL3, bit [5]
When FEAT_GCS is implemented:

AMAIR2_EL3, bit [4]
When FEAT_AIE is implemented: