MAIR_EL3, Memory Attribute Indirection Register (EL3)

The MAIR_EL3 characteristics are:

Purpose

Provides the memory attribute encodings corresponding to the possible AttrIndx values in a Long-descriptor format translation table entry for stage 1 translations at EL3.

Configuration

This register is present only when EL3 is implemented. Otherwise, direct accesses to MAIR_EL3 are UNDEFINED.

Attributes

MAIR_EL3 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
Attr7Attr6Attr5Attr4
Attr3Attr2Attr1Attr0

MAIR_EL3 is permitted to be cached in a TLB.

Attr<n>, bits [8n+7:8n], for n = 7 to 0

Memory Attribute encoding.

When FEAT_AIE is implemented and stage 1 Attributes Index Extension is enabled and AttrIndx[3] in a Long descriptor format translation table entry is 0, or when FEAT_AIE is not implemented, AttrIndx[2:0] gives the value of <n> in Attr<n>.

When FEAT_AIE is implemented and stage 1 Attributes Index Extension is enabled and AttrIndx[3] in a Long descriptor format translation table entry is 1, see MAIR2_EL3.Attr

Attr is encoded as follows:

AttrMeaning
0b0000dd00Device memory. See encoding of 'dd' for the type of Device memory.
0b0000dd01If FEAT_XS is implemented: Device memory with the XS attribute set to 0. See encoding of 'dd' for the type of Device memory. Otherwise,UNPREDICTABLE.
0b0000dd1xUNPREDICTABLE.
0booooiiiiwhere oooo != 0000 and iiii != 0000Normal memory. See encoding of 'oooo' and 'iiii' for the type of Normal memory.
0b01000000If FEAT_XS is implemented: Normal Inner Non-cacheable, Outer Non-cacheable memory with the XS attribute set to 0. Otherwise,UNPREDICTABLE.
0b10100000If FEAT_XS is implemented: Normal Inner Write-through Cacheable, Outer Write-through Cacheable, Read-Allocate, No-Write Allocate, Non-transient memory with the XS attribute set to 0. Otherwise,UNPREDICTABLE.
0b11110000If FEAT_MTE2 is implemented: Tagged Normal Inner Write-Back, Outer Write-Back, Read-Allocate, Write-Allocate Non-transient memory. Otherwise,UNPREDICTABLE.
0bxxxx0000where xxxx != 0000 and xxxx != 0100 and xxxx != 1010 and xxxx != 1111UNPREDICTABLE.

dd is encoded as follows:

'dd'Meaning
0b00Device-nGnRnE memory.
0b01Device-nGnRE memory.
0b10Device-nGRE memory.
0b11Device-GRE memory.

oooo is encoded as follows:

'oooo'Meaning
0b0000See encoding of Attr.
0b00RWwhere RW != 00Normal memory, Outer Write-Through Transient.
0b0100Normal memory, Outer Non-cacheable.
0b01RWwhere RW != 00Normal memory, Outer Write-Back Transient.
0b10RWNormal memory, Outer Write-Through Non-transient.
0b11RWNormal memory, Outer Write-Back Non-transient.

R encodes the Outer Read-Allocate policy and W encodes the Outer Write-Allocate policy.

iiii is encoded as follows:

'iiii'Meaning
0b0000See encoding of Attr.
0b00RWwhere RW != 00Normal memory, Inner Write-Through Transient.
0b0100Normal memory, Inner Non-cacheable.
0b01RWwhere RW != 00Normal memory, Inner Write-Back Transient.
0b10RWNormal memory, Inner Write-Through Non-transient.
0b11RWNormal memory, Inner Write-Back Non-transient.

R encodes the Inner Read-Allocate policy and W encodes the Inner Write-Allocate policy.

In oooo and iiii, R and W are encoded as follows:

'R' or 'W'Meaning
0b0No Allocate.
0b1Allocate.

When FEAT_XS is implemented, stage 1 Inner Write-Back Cacheable, Outer Write-Back Cacheable memory types have the XS attribute set to 0.

The reset behavior of this field is:

Accessing MAIR_EL3

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, MAIR_EL3

op0op1CRnCRmop2
0b110b1100b10100b00100b000

if !HaveEL(EL3) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then X[t, 64] = MAIR_EL3;

MSR MAIR_EL3, <Xt>

op0op1CRnCRmop2
0b110b1100b10100b00100b000

if !HaveEL(EL3) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_FGWTE3) && FGWTE3_EL3.MAIR_EL3 == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else MAIR_EL3 = X[t, 64];


15/12/2024 22:27; 5e0a212688c6bd7aee92394b6f5e491b4d0fee1d

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