PMITCTRL

Enables the Performance Monitors to switch from default mode into integration mode, where test software can control directly the inputs and outputs of the PE, for integration testing or topology detection.

Configuration

This register is present only when FEAT_PMUv3_EXT is implemented and an implementation implements PMITCTRL. Otherwise, direct accesses to PMITCTRL are RES0.

Attributes

Field descriptions

Bits [31:1]

IME, bit [0]

Integration mode enable. When IME == 1, the device reverts to an integration mode to enable integration testing or topology detection.

IME	Meaning
0b0	Normal operation.
0b1	Integration mode enabled.

The integration mode behavior is IMPLEMENTATION DEFINED.

The following resets apply:

If the register is implemented in the Core power domain:
- On a Cold reset, this field resets to 0.
- On an External debug reset, the value of this field is unchanged.
- On a Warm reset, the value of this field is unchanged.
If the register is implemented in the External debug power domain:
- On a Cold reset, the value of this field is unchanged.
- On an External debug reset, this field resets to 0.
- On a Warm reset, the value of this field is unchanged.

Accessing PMITCTRL

Accesses to this register use the following encodings:

Accessible at offset 0xF00 from PMU

When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(), accesses to this register generate an error response.
When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(), or PMCCR.OSLO == 0) and OSLockStatus(), accesses to this register generate an error response.
When SoftwareLockStatus(), accesses to this register are RO.
Otherwise, accesses to this register are RW.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																															IME