PMEVFILT2R<n>, Performance Monitors Event Filter Registers, n = 0 - 63
The PMEVFILT2R<n> characteristics are:
Purpose
Provides additional IMPLEMENTATION DEFINED configuration controls for PMU counters.
Each PMEVFILT2R<n> register can provide additional configuration controls for a PMU counter, where:
- For values of n less than 31, if event counter n is implemented, then the controls are for PMU event counter <n>.
- For n equal to 31, the controls are for the cycle counter, PMCCNTR_EL0;
- For n equal to 32, if FEAT_PMUv3_ICNTR is implemented, the controls are for the instruction counter, PMICNTR_EL0;
- For all other values of n, PMEVFILT2R<n> is not implemented.
Although this mapping is recommended, it is not required and the function of each register is IMPLEMENTATION DEFINED.
Configuration
This register is present only when FEAT_PMUv3_EXT is implemented and an implementation implements PMEVFILT2R<n>. Otherwise, direct accesses to PMEVFILT2R<n> are RES0.
PMEVFILT2R<n> is in the Core power domain.
If PMEVFILT2R<n> is not implemented:
- When IsCorePowered() && !DoubleLockStatus() && !OSLockStatus() && AllowExternalPMUAccess(), accesses are RES0.
- Otherwise, it is CONSTRAINED UNPREDICTABLE whether accesses to this register are RES0 or generate an error response.
Attributes
PMEVFILT2R<n> is a:
- 64-bit register when FEAT_PMUv3_EXT64 is implemented
- 32-bit register otherwise
This register is part of the PMU block.
Field descriptions
When FEAT_PMUv3_EXT64 is implemented:
IMPLEMENTATION DEFINED, bits [63:0]
Otherwise:
IMPLEMENTATION DEFINED, bits [31:0]
Accessing PMEVFILT2R<n>
SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.
Accesses to this register use the following encodings:
When FEAT_PMUv3_EXT32 is implemented
[31:0] Accessible at offset 0x800 + (4 * n) from PMU
- When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(), accesses to this register generate an error response.
- When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(), or PMCCR.OSLO == 0) and OSLockStatus(), accesses to this register generate an error response.
- When FEAT_PMUv3_EXTPMN is implemented, IsRange3Counter(n), and !IsMostSecureAccess(), accesses to this register are RAZ/WI.
- When SoftwareLockStatus(), accesses to this register are RO.
- Otherwise, accesses to this register are RW.
When FEAT_PMUv3_EXT64 is implemented
[63:0] Accessible at offset 0x800 + (8 * n) from PMU
- When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(), accesses to this register generate an error response.
- When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(), or PMCCR.OSLO == 0) and OSLockStatus(), accesses to this register generate an error response.
- When FEAT_PMUv3_EXTPMN is implemented, IsRange3Counter(n), and !IsMostSecureAccess(), accesses to this register are RAZ/WI.
- Otherwise, accesses to this register are RW.
15/12/2024 22:27; 5e0a212688c6bd7aee92394b6f5e491b4d0fee1d
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