The PMDEVAFF characteristics are:
Copy of the PE MPIDR_EL1 register that allows a debugger to determine which PE in a multiprocessor system the Performance Monitor component relates to.
This register is present only when FEAT_PMUv3_EXT64 is implemented. Otherwise, direct accesses to PMDEVAFF are RES0.
PMDEVAFF is a 64-bit register.
This register is part of the PMU block.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | Aff3 | ||||||||||||||||||||||||||||||
| RAO/WI | U | RES0 | MT | Aff2 | Aff1 | Aff0 | |||||||||||||||||||||||||
Reserved, RES0.
Affinity level 3. See the description of Aff0 for more information.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Reserved, RAO/WI.
Indicates a Uniprocessor system, as distinct from PE 0 in a multiprocessor system.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| U | Meaning |
|---|---|
| 0b0 |
Processor is part of a multiprocessor system. |
| 0b1 |
Processor is part of a uniprocessor system. |
Access to this field is RO.
Reserved, RES0.
Indicates whether the lowest level of affinity consists of logical PEs that are implemented using an interdependent approach, such as multithreading. See the description of Aff0 for more information about affinity levels.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| MT | Meaning |
|---|---|
| 0b0 |
Performance of PEs with different affinity level 0 values, and the same values for affinity level 1 and higher, is largely independent. |
| 0b1 |
Performance of PEs with different affinity level 0 values, and the same values for affinity level 1 and higher, is very interdependent. |
This field does not indicate that multithreading is implemented and does not indicate that PEs with different affinity level 0 values, and the same values for affinity level 1 and higher are implemented.
Access to this field is RO.
Affinity level 2. See the description of Aff0 for more information.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Affinity level 1. See the description of Aff0 for more information.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Affinity level 0. The value of the MPIDR.{Aff2, Aff1, Aff0} or MPIDR_EL1.{Aff3, Aff2, Aff1, Aff0} set of fields of each PE must be unique within the system as a whole.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Accesses to this register use the following encodings:
Accessible at offset 0xFA8 from PMU
15/12/2024 22:27; 5e0a212688c6bd7aee92394b6f5e491b4d0fee1d
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