PMCCNTSVR_EL1, Performance Monitors Cycle Count Saved Value Register

The PMCCNTSVR_EL1 characteristics are:

Purpose

Captures the PMU Cycle counter, PMCCNTR_EL0.

External register PMCCNTSVR_EL1 bits [63:0] are architecturally mapped to AArch64 System register PMCCNTSVR_EL1[63:0].

This register is present only when FEAT_PMUv3_SS is implemented. Otherwise, direct accesses to PMCCNTSVR_EL1 are RES0.

PMCCNTSVR_EL1 is a 64-bit register.

This register is part of the PMU block.

Sampled Cycle Count. The value of PMCCNTR_EL0 at the last successful Capture event.

The reset behavior of this field is:

On a Cold reset, when FEAT_PMUv3_EXTPMN is implemented, this field resets to an architecturally UNKNOWN value.
On a Warm reset, when FEAT_PMUv3_EXTPMN is not implemented, this field resets to an architecturally UNKNOWN value.

Accesses to this register use the following encodings:

Accessible at offset 0x6F8 from PMU

When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMSSAccess(), accesses to this register generate an error response.
Otherwise, accesses to this register are RO.

15/12/2024 22:27; 5e0a212688c6bd7aee92394b6f5e491b4d0fee1d