The GICD_IGRPMODR<n>E characteristics are:
When GICD_CTLR.DS==0, this register together with the GICD_IGROUPR<n>E registers, controls whether the corresponding interrupt is in:
This register is present only when GICv3.1 is implemented. Otherwise, direct accesses to GICD_IGRPMODR<n>E are RES0.
GICD_IGRPMODR<n>E resets to 0x00000000.
When GICD_TYPER.ESPI==0, these registers are RES0.
When GICD_TYPER.ESPI==1:
GICD_IGRPMODR<n>E is a 32-bit register.
Group modifier bit. In implementations where affinity routing is enabled for the Security state of an interrupt, the bit that corresponds to the interrupt is concatenated with the equivalent bit in GICD_IGROUPR<n>E to form a 2-bit field that defines an interrupt group:
| Group modifier bit | Group status bit | Definition | Short name |
|---|---|---|---|
| 0b0 | 0b0 | Secure Group 0 | G0S |
| 0b0 | 0b1 | Non-secure Group 1 | G1NS |
| 0b1 | 0b0 | Secure Group 1 | G1S |
| 0b1 | 0b1 | Reserved, treated as Non-secure Group 1 | - |
The reset behavior of this field is:
For INTID m, when DIV and MOD are the integer division and modulo operations:
When affinity routing is not enabled for the Security state of an interrupt in GICD_IGRPMODR<n>E, the corresponding bit is RES0.
When GICD_CTLR.DS==0, bits corresponding to Secure SPIs are RAZ/WI to Non-secure accesses.
Bits corresponding to unimplemented interrupts are RAZ/WI.
| Component | Frame | Offset | Instance |
|---|---|---|---|
| GIC Distributor | Dist_base | 0x3400 + (4 * n) | GICD_IGRPMODR<n>E |
Accesses to this register are RW.
15/12/2024 22:27; 5e0a212688c6bd7aee92394b6f5e491b4d0fee1d
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.