GICD_CLRSPI_SR, Clear Secure SPI Pending Register

The GICD_CLRSPI_SR characteristics are:

Purpose

Removes the pending state from a valid SPI.

A write to this register changes the state of a pending SPI to inactive, and the state of an active and pending SPI to active.

Configuration

If GICD_TYPER.MBIS == 0, this register is reserved.

When GICD_CTLR.DS == 1, this register is WI.

Attributes

GICD_CLRSPI_SR is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
RES0INTID

Bits [31:13]

Reserved, RES0.

INTID, bits [12:0]

The INTID of the SPI.

Additional information

The function of this register depends on whether the targeted SPI is configured to be an edge-triggered or level-sensitive interrupt:

Accessing GICD_CLRSPI_SR

Writes to this register have no effect if:

16-bit accesses to bits [15:0] of this register must be supported.

GICD_CLRSPI_SR can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
GIC DistributorDist_base0x0058GICD_CLRSPI_SR

Accessible as follows:


15/12/2024 22:27; 5e0a212688c6bd7aee92394b6f5e491b4d0fee1d

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