AMDEVAFF1

Copy of the high half of the PE MPIDR_EL1 register that allows a debugger to determine which PE in a multiprocessor system the AMU component relates to.

Configuration

It is IMPLEMENTATION DEFINED whether AMDEVAFF1 is implemented in the Core power domain or in the Debug power domain.

This register is present only when FEAT_AMUv1 is implemented, FEAT_AMU_EXT32 is implemented, and an implementation implements AMDEVAFF1. Otherwise, direct accesses to AMDEVAFF1 are RES0.

Attributes

Field descriptions

Bits [31:8]

Aff3, bits [7:0]

Affinity level 3. See the description of AMDEVAFF0.Aff0 for more information.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Accessing AMDEVAFF1

Accesses to this register use the following encodings:

Accessible at offset 0xFAC from AMU

When boolean IMPLEMENTATION_DEFINED "AMU CoreSight management registers ignore access controls", accesses to this register are RO.
When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Secure, and AMROOTCR.RA IN {0b01, 0b00}, accesses to this register are RAZ/WI.
When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Realm, and AMROOTCR.RA IN {0b10, 0b00}, accesses to this register are RAZ/WI.
When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMROOTCR.RA != 0b11, accesses to this register are RAZ/WI.
When FEAT_RME is not implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMSCR.NSRA == 0, accesses to this register are RAZ/WI.
Otherwise, accesses to this register are RO.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																								Aff3