TCR2_EL2

This register is present only when FEAT_TCR2 is implemented. Otherwise, direct accesses to TCR2_EL2 are UNDEFINED.

Attributes

Field descriptions

When !ELIsInHost(EL2):

Bits [63:13]

AMEC0, bit [12]
When FEAT_MEC is implemented:

This field controls the enabling of the Alternate MECID translations for the EL2 translation regime.

TCR2_EL2.AMEC0 is provided to enable the safe update of MECID_A0_EL2, by disabling access and speculation to AMEC==1 Block or Page descriptors during the update.

AMEC0	Meaning
0b0	Use of a Block or Page descriptor containing AMEC == 1 generates a Translation fault.
0b1	Accesses translated by a Block or Page descriptor containing AMEC == 1 are associated with the MECID configured in MECID_A0_EL2.

This bit is permitted to be cached in a TLB only if it is 1.

When EL3 is implemented and SCR_EL3.TCR2En == 0, this field is ignored by the PE and treated as zero.

When SCTLR2_EL2.EMEC is 0, this field is ignored by the PE and the bit position of AMEC is RES0 in Block and Page descriptors.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing this field has the following behavior:

When IsCurrentSecurityState(SS_Secure), access to this field is RES0 .
When IsCurrentSecurityState(SS_NonSecure), access to this field is RES0 .

Otherwise:

HAFT, bit [11]
When FEAT_HAFT is implemented:

HAFT	Meaning
0b0	Hardware managed Access Flag for Table descriptors is disabled.
0b1	Hardware managed Access Flag for Table descriptors is enabled.

Otherwise:

PTTWI, bit [10]
When FEAT_THE is implemented:

Permit Translation table walk Incoherence.

Permits RCWS instructions to generate writes that have the Reduced Coherence property.

PTTWI	Meaning
0b0	Write accesses generated by RCWS at EL2 or EL2&0 do not have the Reduced Coherence property.
0b1	Write accesses generated by RCWS at EL2 or EL2&0 have the Reduced Coherence property.

This bit is permitted to be implemented as a read-only bit with a fixed value of 0.

When EL3 is implemented and SCR_EL3.TCR2En == 0, this field is ignored by the PE and treated as zero.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bits [9:5]

AIE, bit [4]
When FEAT_AIE is implemented:

AIE	Meaning
0b0	Attribute Indexing Extension Disabled.
0b1	Attribute Indexing Extension Enabled.

Otherwise:

POE, bit [3]
When FEAT_S1POE is implemented:

POE	Meaning
0b0	Permission overlay disabled for EL2 access in stage 1 of EL2 translation regime.
0b1	Permission overlay enabled for EL2 access in stage 1 of EL2 translation regime.

Otherwise:

Bit [2]

PIE, bit [1]
When FEAT_S1PIE is implemented:

PIE	Meaning
0b0	Direct permission model.
0b1	Indirect permission model.

Otherwise:

PnCH, bit [0]
When FEAT_THE is implemented:

PnCH	Meaning
0b0	Bit[52] of each stage 1 translation table entry does not indicate protected attribute.
0b1	Bit[52] of each stage 1 translation table entry indicates protected attribute.

Otherwise:

When ELIsInHost(EL2):

Bits [63:19]

FNG1, bit [18]
When FEAT_ASID2 is implemented:

FNG1	Meaning
0b0	This bit has no effect on the interpretation of the nG bit.
0b1	Translations are treated as non-global regardless of the value of the nG bit.

Otherwise:

FNG0, bit [17]
When FEAT_ASID2 is implemented:

FNG0	Meaning
0b0	This bit has no effect on the interpretation of the nG bit.
0b1	Translations are treated as non-global regardless of the value of the nG bit.

Otherwise:

A2, bit [16]
When FEAT_ASID2 is implemented:

A2	Meaning
0b0	Use of two ASIDs is disabled.
0b1	Use of two ASIDs is enabled.

Otherwise:

DisCH1, bit [15]
When FEAT_D128 is implemented and TCR2_EL2.D128 == 1:

DisCH1	Meaning
0b0	The Contiguous bit of Block or Page descriptors of the Start Table for TTBR1_EL2 is not affected by this field.
0b1	The Contiguous bit of Block or Page descriptors of the Start Table for TTBR1_EL2 is treated as 0.

Otherwise:

DisCH0, bit [14]
When FEAT_D128 is implemented and TCR2_EL2.D128 == 1:

DisCH0	Meaning
0b0	The Contiguous bit of Block or Page descriptors of the Start Table for TTBR0_EL2 is not affected by this field.
0b1	The Contiguous bit of Block or Page descriptors of the Start Table for TTBR0_EL2 is treated as 0.

Otherwise:

AMEC1, bit [13]
When FEAT_MEC is implemented:

This field controls the enabling of the Alternate MECID translations for accesses in the TTBR1_EL2 half of the VA range, for the EL2&0 translation regime.

TCR2_EL2.AMEC1 is provided to enable the safe update of MECID_A1_EL2, by disabling access and speculation to AMEC == 1 Block or Page descriptors during the update.

AMEC1	Meaning
0b0	Use of a Block or Page descriptor containing AMEC == 1 generates a Translation fault.
0b1	Accesses translated by a Block or Page descriptor containing AMEC == 1 are associated with the MECID configured in MECID_A1_EL2.

This bit is permitted to be cached in a TLB only if it is 1.

When EL3 is implemented and SCR_EL3.TCR2En == 0, this field is ignored by the PE and treated as zero.

When SCTLR2_EL2.EMEC is 0, this field is ignored by the PE and the bit position of AMEC is RES0 in Block and Page descriptors.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing this field has the following behavior:

When IsCurrentSecurityState(SS_Secure), access to this field is RES0 .
When IsCurrentSecurityState(SS_NonSecure), access to this field is RES0 .

Otherwise:

AMEC0, bit [12]
When FEAT_MEC is implemented:

This field controls the enabling of the Alternate MECID translations for accesses in the TTBR0_EL2 half of the VA range, for the EL2&0 translation regime.

TCR2_EL2.AMEC0 is provided to enable the safe update of MECID_A0_EL2, by disabling access and speculation to AMEC==1 Block or Page descriptors during the update.

AMEC0	Meaning
0b0	Use of a Block or Page descriptor containing AMEC == 1 generates a Translation fault.
0b1	Accesses translated by a Block or Page descriptor containing AMEC == 1 are associated with the MECID configured in MECID_A0_EL2.

This bit is permitted to be cached in a TLB only if it is 1.

When EL3 is implemented and SCR_EL3.TCR2En == 0, this field is ignored by the PE and treated as zero.

When SCTLR2_EL2.EMEC is 0, this field is ignored by the PE and the bit position of AMEC is RES0 in Block and Page descriptors.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing this field has the following behavior:

When IsCurrentSecurityState(SS_Secure), access to this field is RES0 .
When IsCurrentSecurityState(SS_NonSecure), access to this field is RES0 .

Otherwise:

HAFT, bit [11]
When FEAT_HAFT is implemented:

HAFT	Meaning
0b0	Hardware managed Access Flag for Table descriptors is disabled.
0b1	Hardware managed Access Flag for Table descriptors is enabled.

Otherwise:

PTTWI, bit [10]
When FEAT_THE is implemented:

Permit Translation table walk Incoherence.

Permits RCWS instructions to generate writes that have the Reduced Coherence property.

PTTWI	Meaning
0b0	Write accesses generated by RCWS do not have the Reduced Coherence property.
0b1	Write accesses generated by RCWS have the Reduced Coherence property.

This bit is permitted to be implemented as a read-only bit with a fixed value of 0.

When EL3 is implemented and SCR_EL3.TCR2En == 0, this field is ignored by the PE and treated as zero.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bits [9:6]

D128, bit [5]
When FEAT_D128 is implemented:

D128	Meaning
0b0	Translation system follows VMSAv8-64 translation process.
0b1	Translation system follows VMSAv9-128 translation process.

Otherwise:

AIE, bit [4]
When FEAT_AIE is implemented:

AIE	Meaning
0b0	Attribute Indexing Extension Disabled.
0b1	Attribute Indexing Extension Enabled.

Otherwise:

POE, bit [3]
When FEAT_S1POE is implemented:

POE	Meaning
0b0	Permission overlay disabled for EL2 access in stage 1 of EL2&0 translation regime.
0b1	Permission overlay enabled for EL2 access in stage 1 of EL2&0 translation regime.

Otherwise:

E0POE, bit [2]
When FEAT_S1POE is implemented:

E0POE	Meaning
0b0	Permission overlay disabled for EL0 access in stage 1 of EL2&0 translation regime.
0b1	Permission overlay enabled for EL0 access in stage 1 of EL2&0 translation regime.

Otherwise:

PIE, bit [1]
When FEAT_S1PIE is implemented:

PIE	Meaning
0b0	Direct permission model.
0b1	Indirect permission model.

Otherwise:

PnCH, bit [0]
When FEAT_THE is implemented:

PnCH	Meaning
0b0	Bit[52] of each stage 1 translation table entry does not indicate protected attribute.
0b1	Bit[52] of each stage 1 translation table entry indicate protected attribute.

Otherwise:

Accessing TCR2_EL2

When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL2 using the accessor name TCR2_EL2 or TCR2_EL1 are not guaranteed to be ordered with respect to accesses using the other accessor name.

If FEAT_SRMASK is implemented, accesses to TCR2_EL2 are masked by TCR2MASK_EL2.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, TCR2_EL2

op0	op1	CRn	CRm	op2
0b11	0b100	0b0010	0b0000	0b011

if !IsFeatureImplemented(FEAT_TCR2) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.TCR2En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.TCR2En == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = TCR2_EL2; elsif PSTATE.EL == EL3 then X[t, 64] = TCR2_EL2;

MSR TCR2_EL2, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b100	0b0010	0b0000	0b011

if !IsFeatureImplemented(FEAT_TCR2) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.TCR2En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.TCR2En == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else if IsFeatureImplemented(FEAT_SRMASK) then TCR2_EL2 = (X[t, 64] AND NOT EffectiveTCR2MASK_EL2()) OR (TCR2_EL2 AND EffectiveTCR2MASK_EL2()); else TCR2_EL2 = X[t, 64]; elsif PSTATE.EL == EL3 then TCR2_EL2 = X[t, 64];

MRS <Xt>, TCR2_EL1

op0	op1	CRn	CRm	op2
0b11	0b000	0b0010	0b0000	0b011

if !IsFeatureImplemented(FEAT_TCR2) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.TCR2En == '0' then UNDEFINED; elsif EL2Enabled() && HCR_EL2.TRVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.TCR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.TCR2En == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.TCR2En == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then X[t, 64] = NVMem[0x270]; else X[t, 64] = TCR2_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.TCR2En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.TCR2En == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif ELIsInHost(EL2) then X[t, 64] = TCR2_EL2; else X[t, 64] = TCR2_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = TCR2_EL1;

MSR TCR2_EL1, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b000	0b0010	0b0000	0b011

if !IsFeatureImplemented(FEAT_TCR2) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.TCR2En == '0' then UNDEFINED; elsif EL2Enabled() && HCR_EL2.TVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGWTR_EL2.TCR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.TCR2En == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.TCR2En == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem[0x270] = X[t, 64]; else if IsFeatureImplemented(FEAT_SRMASK) then TCR2_EL1 = (X[t, 64] AND NOT EffectiveTCR2MASK_EL1()) OR (TCR2_EL1 AND EffectiveTCR2MASK_EL1()); else TCR2_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.TCR2En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.TCR2En == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif ELIsInHost(EL2) then if IsFeatureImplemented(FEAT_SRMASK) then TCR2_EL2 = (X[t, 64] AND NOT EffectiveTCR2MASK_EL2()) OR (TCR2_EL2 AND EffectiveTCR2MASK_EL2()); else TCR2_EL2 = X[t, 64]; else TCR2_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then TCR2_EL1 = X[t, 64];

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0																			AMEC0	HAFT	PTTWI	RES0					AIE	POE	RES0	PIE	PnCH

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0													FNG1	FNG0	A2	DisCH1	DisCH0	AMEC1	AMEC0	HAFT	PTTWI	RES0				D128	AIE	POE	E0POE	PIE	PnCH

TCR2_EL2, Extended Translation Control Register (EL2)

Purpose

Configuration

Attributes

Field descriptions

When !ELIsInHost(EL2):

Bits [63:13]

AMEC0, bit [12]When FEAT_MEC is implemented:

Otherwise:

HAFT, bit [11]When FEAT_HAFT is implemented:

Otherwise:

PTTWI, bit [10]When FEAT_THE is implemented:

Otherwise:

Bits [9:5]

AIE, bit [4]When FEAT_AIE is implemented:

Otherwise:

POE, bit [3]When FEAT_S1POE is implemented:

Otherwise:

Bit [2]

PIE, bit [1]When FEAT_S1PIE is implemented:

Otherwise:

PnCH, bit [0]When FEAT_THE is implemented:

Otherwise:

When ELIsInHost(EL2):

Bits [63:19]

FNG1, bit [18]When FEAT_ASID2 is implemented:

Otherwise:

FNG0, bit [17]When FEAT_ASID2 is implemented:

Otherwise:

A2, bit [16]When FEAT_ASID2 is implemented:

Otherwise:

DisCH1, bit [15]When FEAT_D128 is implemented and TCR2_EL2.D128 == 1:

Otherwise:

DisCH0, bit [14]When FEAT_D128 is implemented and TCR2_EL2.D128 == 1:

Otherwise:

AMEC1, bit [13]When FEAT_MEC is implemented:

Otherwise:

AMEC0, bit [12]When FEAT_MEC is implemented:

Otherwise:

HAFT, bit [11]When FEAT_HAFT is implemented:

Otherwise:

PTTWI, bit [10]When FEAT_THE is implemented:

Otherwise:

Bits [9:6]

D128, bit [5]When FEAT_D128 is implemented:

Otherwise:

AIE, bit [4]When FEAT_AIE is implemented:

Otherwise:

POE, bit [3]When FEAT_S1POE is implemented:

Otherwise:

E0POE, bit [2]When FEAT_S1POE is implemented:

Otherwise:

PIE, bit [1]When FEAT_S1PIE is implemented:

Otherwise:

PnCH, bit [0]When FEAT_THE is implemented:

Otherwise:

Accessing TCR2_EL2

MRS <Xt>, TCR2_EL2

MSR TCR2_EL2, <Xt>

MRS <Xt>, TCR2_EL1

MSR TCR2_EL1, <Xt>

AMEC0, bit [12]
When FEAT_MEC is implemented:

HAFT, bit [11]
When FEAT_HAFT is implemented:

PTTWI, bit [10]
When FEAT_THE is implemented:

AIE, bit [4]
When FEAT_AIE is implemented:

POE, bit [3]
When FEAT_S1POE is implemented:

PIE, bit [1]
When FEAT_S1PIE is implemented:

PnCH, bit [0]
When FEAT_THE is implemented:

FNG1, bit [18]
When FEAT_ASID2 is implemented:

FNG0, bit [17]
When FEAT_ASID2 is implemented:

A2, bit [16]
When FEAT_ASID2 is implemented:

DisCH1, bit [15]
When FEAT_D128 is implemented and TCR2_EL2.D128 == 1:

DisCH0, bit [14]
When FEAT_D128 is implemented and TCR2_EL2.D128 == 1:

AMEC1, bit [13]
When FEAT_MEC is implemented:

AMEC0, bit [12]
When FEAT_MEC is implemented:

HAFT, bit [11]
When FEAT_HAFT is implemented:

PTTWI, bit [10]
When FEAT_THE is implemented:

D128, bit [5]
When FEAT_D128 is implemented:

AIE, bit [4]
When FEAT_AIE is implemented:

POE, bit [3]
When FEAT_S1POE is implemented:

E0POE, bit [2]
When FEAT_S1POE is implemented:

PIE, bit [1]
When FEAT_S1PIE is implemented:

PnCH, bit [0]
When FEAT_THE is implemented: