SCTLRMASK

This register is present only when FEAT_SRMASK is implemented. Otherwise, direct accesses to SCTLRMASK_EL2 are UNDEFINED.

This register has no effect if EL2 is not enabled in the current Security state.

Attributes

Field descriptions

TIDCP, bit [63]
When FEAT_TIDCP1 is implemented:

TIDCP	Meaning
0b0	SCTLR_EL2.TIDCP is writeable.
0b1	SCTLR_EL2.TIDCP is not writeable.

Otherwise:

SPINTMASK, bit [62]
When FEAT_NMI is implemented:

SPINTMASK	Meaning
0b0	SCTLR_EL2.SPINTMASK is writeable.
0b1	SCTLR_EL2.SPINTMASK is not writeable.

Otherwise:

NMI, bit [61]
When FEAT_NMI is implemented:

NMI	Meaning
0b0	SCTLR_EL2.NMI is writeable.
0b1	SCTLR_EL2.NMI is not writeable.

Otherwise:

EnTP2, bit [60]
When FEAT_SME is implemented:

EnTP2	Meaning
0b0	SCTLR_EL2.EnTP2 is writeable.
0b1	SCTLR_EL2.EnTP2 is not writeable.

Otherwise:

TCSO, bit [59]
When FEAT_MTE_STORE_ONLY is implemented:

TCSO	Meaning
0b0	SCTLR_EL2.TCSO is writeable.
0b1	SCTLR_EL2.TCSO is not writeable.

Otherwise:

TCSO0, bit [58]
When FEAT_MTE_STORE_ONLY is implemented:

TCSO0	Meaning
0b0	SCTLR_EL2.TCSO0 is writeable.
0b1	SCTLR_EL2.TCSO0 is not writeable.

Otherwise:

EPAN, bit [57]
When FEAT_PAN3 is implemented:

EPAN	Meaning
0b0	SCTLR_EL2.EPAN is writeable.
0b1	SCTLR_EL2.EPAN is not writeable.

Otherwise:

EnALS, bit [56]
When FEAT_LS64 is implemented:

EnALS	Meaning
0b0	SCTLR_EL2.EnALS is writeable.
0b1	SCTLR_EL2.EnALS is not writeable.

Otherwise:

EnAS0, bit [55]
When FEAT_LS64_ACCDATA is implemented:

EnAS0	Meaning
0b0	SCTLR_EL2.EnAS0 is writeable.
0b1	SCTLR_EL2.EnAS0 is not writeable.

Otherwise:

EnASR, bit [54]
When FEAT_LS64_V is implemented:

EnASR	Meaning
0b0	SCTLR_EL2.EnASR is writeable.
0b1	SCTLR_EL2.EnASR is not writeable.

Otherwise:

TME, bit [53]
When FEAT_TME is implemented:

TME	Meaning
0b0	SCTLR_EL2.TME is writeable.
0b1	SCTLR_EL2.TME is not writeable.

Otherwise:

TME0, bit [52]
When FEAT_TME is implemented:

TME0	Meaning
0b0	SCTLR_EL2.TME0 is writeable.
0b1	SCTLR_EL2.TME0 is not writeable.

Otherwise:

TMT, bit [51]
When FEAT_TME is implemented:

TMT	Meaning
0b0	SCTLR_EL2.TMT is writeable.
0b1	SCTLR_EL2.TMT is not writeable.

Otherwise:

TMT0, bit [50]
When FEAT_TME is implemented:

TMT0	Meaning
0b0	SCTLR_EL2.TMT0 is writeable.
0b1	SCTLR_EL2.TMT0 is not writeable.

Otherwise:

Bits [49:47]

TWEDEL, bit [46]
When FEAT_TWED is implemented:

TWEDEL	Meaning
0b0	SCTLR_EL2.TWEDEL is writeable.
0b1	SCTLR_EL2.TWEDEL is not writeable.

Otherwise:

TWEDEn, bit [45]
When FEAT_TWED is implemented:

TWEDEn	Meaning
0b0	SCTLR_EL2.TWEDEn is writeable.
0b1	SCTLR_EL2.TWEDEn is not writeable.

Otherwise:

DSSBS, bit [44]
When FEAT_SSBS is implemented:

DSSBS	Meaning
0b0	SCTLR_EL2.DSSBS is writeable.
0b1	SCTLR_EL2.DSSBS is not writeable.

Otherwise:

ATA, bit [43]
When FEAT_MTE2 is implemented:

ATA	Meaning
0b0	SCTLR_EL2.ATA is writeable.
0b1	SCTLR_EL2.ATA is not writeable.

Otherwise:

ATA0, bit [42]
When FEAT_MTE2 is implemented:

ATA0	Meaning
0b0	SCTLR_EL2.ATA0 is writeable.
0b1	SCTLR_EL2.ATA0 is not writeable.

Otherwise:

Bit [41]

TCF, bit [40]
When FEAT_MTE2 is implemented:

TCF	Meaning
0b0	SCTLR_EL2.TCF is writeable.
0b1	SCTLR_EL2.TCF is not writeable.

Otherwise:

Bit [39]

TCF0, bit [38]
When FEAT_MTE2 is implemented:

TCF0	Meaning
0b0	SCTLR_EL2.TCF0 is writeable.
0b1	SCTLR_EL2.TCF0 is not writeable.

Otherwise:

ITFSB, bit [37]
When FEAT_MTE_ASYNC is implemented:

ITFSB	Meaning
0b0	SCTLR_EL2.ITFSB is writeable.
0b1	SCTLR_EL2.ITFSB is not writeable.

Otherwise:

BT, bit [36]
When FEAT_BTI is implemented:

BT	Meaning
0b0	SCTLR_EL2.BT is writeable.
0b1	SCTLR_EL2.BT is not writeable.

Otherwise:

BT0, bit [35]
When FEAT_BTI is implemented:

BT0	Meaning
0b0	SCTLR_EL2.BT0 is writeable.
0b1	SCTLR_EL2.BT0 is not writeable.

Otherwise:

EnFPM, bit [34]
When FEAT_FPMR is implemented:

EnFPM	Meaning
0b0	SCTLR_EL2.EnFPM is writeable.
0b1	SCTLR_EL2.EnFPM is not writeable.

Otherwise:

MSCEn, bit [33]
When FEAT_MOPS is implemented:

MSCEn	Meaning
0b0	SCTLR_EL2.MSCEn is writeable.
0b1	SCTLR_EL2.MSCEn is not writeable.

Otherwise:

CMOW, bit [32]
When FEAT_CMOW is implemented:

CMOW	Meaning
0b0	SCTLR_EL2.CMOW is writeable.
0b1	SCTLR_EL2.CMOW is not writeable.

Otherwise:

EnIA, bit [31]
When FEAT_PAuth is implemented:

EnIA	Meaning
0b0	SCTLR_EL2.EnIA is writeable.
0b1	SCTLR_EL2.EnIA is not writeable.

Otherwise:

EnIB, bit [30]
When FEAT_PAuth is implemented:

EnIB	Meaning
0b0	SCTLR_EL2.EnIB is writeable.
0b1	SCTLR_EL2.EnIB is not writeable.

Otherwise:

LSMAOE, bit [29]
When FEAT_LSMAOC is implemented:

LSMAOE	Meaning
0b0	SCTLR_EL2.LSMAOE is writeable.
0b1	SCTLR_EL2.LSMAOE is not writeable.

Otherwise:

nTLSMD, bit [28]
When FEAT_LSMAOC is implemented:

nTLSMD	Meaning
0b0	SCTLR_EL2.nTLSMD is writeable.
0b1	SCTLR_EL2.nTLSMD is not writeable.

Otherwise:

EnDA, bit [27]
When FEAT_PAuth is implemented:

EnDA	Meaning
0b0	SCTLR_EL2.EnDA is writeable.
0b1	SCTLR_EL2.EnDA is not writeable.

Otherwise:

UCI, bit [26]

UCI	Meaning
0b0	SCTLR_EL2.UCI is writeable.
0b1	SCTLR_EL2.UCI is not writeable.

EE, bit [25]
When FEAT_MixedEnd is implemented:

EE	Meaning
0b0	SCTLR_EL2.EE is writeable.
0b1	SCTLR_EL2.EE is not writeable.

Otherwise:

E0E, bit [24]
When FEAT_MixedEndEL0 is implemented:

E0E	Meaning
0b0	SCTLR_EL2.E0E is writeable.
0b1	SCTLR_EL2.E0E is not writeable.

Otherwise:

SPAN, bit [23]

SPAN	Meaning
0b0	SCTLR_EL2.SPAN is writeable.
0b1	SCTLR_EL2.SPAN is not writeable.

EIS, bit [22]
When FEAT_ExS is implemented:

EIS	Meaning
0b0	SCTLR_EL2.EIS is writeable.
0b1	SCTLR_EL2.EIS is not writeable.

Otherwise:

IESB, bit [21]
When FEAT_IESB is implemented:

IESB	Meaning
0b0	SCTLR_EL2.IESB is writeable.
0b1	SCTLR_EL2.IESB is not writeable.

Otherwise:

TSCXT, bit [20]
When FEAT_CSV2_2 is implemented or FEAT_CSV2_1p2 is implemented:

TSCXT	Meaning
0b0	SCTLR_EL2.TSCXT is writeable.
0b1	SCTLR_EL2.TSCXT is not writeable.

Otherwise:

WXN, bit [19]

nTWE, bit [18]

Bit [17]

nTWI, bit [16]

UCT, bit [15]

DZE, bit [14]

WXN	Meaning
0b0	SCTLR_EL2.WXN is writeable.
0b1	SCTLR_EL2.WXN is not writeable.

nTWE	Meaning
0b0	SCTLR_EL2.nTWE is writeable.
0b1	SCTLR_EL2.nTWE is not writeable.

nTWI	Meaning
0b0	SCTLR_EL2.nTWI is writeable.
0b1	SCTLR_EL2.nTWI is not writeable.

UCT	Meaning
0b0	SCTLR_EL2.UCT is writeable.
0b1	SCTLR_EL2.UCT is not writeable.

DZE	Meaning
0b0	SCTLR_EL2.DZE is writeable.
0b1	SCTLR_EL2.DZE is not writeable.

EnDB, bit [13]
When FEAT_PAuth is implemented:

EnDB	Meaning
0b0	SCTLR_EL2.EnDB is writeable.
0b1	SCTLR_EL2.EnDB is not writeable.

Otherwise:

I, bit [12]

I	Meaning
0b0	SCTLR_EL2.I is writeable.
0b1	SCTLR_EL2.I is not writeable.

EOS, bit [11]
When FEAT_ExS is implemented:

EOS	Meaning
0b0	SCTLR_EL2.EOS is writeable.
0b1	SCTLR_EL2.EOS is not writeable.

Otherwise:

EnRCTX, bit [10]
When FEAT_SPECRES is implemented:

EnRCTX	Meaning
0b0	SCTLR_EL2.EnRCTX is writeable.
0b1	SCTLR_EL2.EnRCTX is not writeable.

Otherwise:

Bit [9]

SED, bit [8]
When EL0 is capable of using AArch32:

Otherwise:

ITD, bit [7]
When EL0 is capable of using AArch32:

Otherwise:

nAA, bit [6]

CP15BEN, bit [5]
When EL0 is capable of using AArch32:

Otherwise:

SA0, bit [4]

SA, bit [3]

C, bit [2]

A, bit [1]

M, bit [0]

Accessing SCTLRMASK_EL2

When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL2 using the accessor name SCTLRMASK_EL2 or SCTLRMASK_EL1 are not guaranteed to be ordered with respect to accesses using the other accessor name.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, SCTLRMASK_EL2

op0	op1	CRn	CRm	op2
0b11	0b100	0b0001	0b0100	0b000

if !IsFeatureImplemented(FEAT_SRMASK) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = SCTLRMASK_EL2; elsif PSTATE.EL == EL3 then X[t, 64] = SCTLRMASK_EL2;

MSR SCTLRMASK_EL2, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b100	0b0001	0b0100	0b000

if !IsFeatureImplemented(FEAT_SRMASK) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif !IsZero(EffectiveSCTLRMASK_EL2()) then UNDEFINED; else SCTLRMASK_EL2 = X[t, 64]; elsif PSTATE.EL == EL3 then SCTLRMASK_EL2 = X[t, 64];

MRS <Xt>, SCTLRMASK_EL1

op0	op1	CRn	CRm	op2
0b11	0b000	0b0001	0b0100	0b000

if !IsFeatureImplemented(FEAT_SRMASK) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3.FGTEn2 == '0') || HFGRTR2_EL2.nSCTLRMASK_EL1 == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.SRMASKEn == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then X[t, 64] = NVMem[0x318]; else X[t, 64] = SCTLRMASK_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif ELIsInHost(EL2) then X[t, 64] = SCTLRMASK_EL2; else X[t, 64] = SCTLRMASK_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = SCTLRMASK_EL1;

MSR SCTLRMASK_EL1, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b000	0b0001	0b0100	0b000

if !IsFeatureImplemented(FEAT_SRMASK) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3.FGTEn2 == '0') || HFGWTR2_EL2.nSCTLRMASK_EL1 == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.SRMASKEn == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem[0x318] = X[t, 64]; elsif !IsZero(EffectiveSCTLRMASK_EL1()) then UNDEFINED; else SCTLRMASK_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif ELIsInHost(EL2) then if !IsZero(EffectiveSCTLRMASK_EL2()) then UNDEFINED; else SCTLRMASK_EL2 = X[t, 64]; else SCTLRMASK_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then SCTLRMASK_EL1 = X[t, 64];

SED	Meaning
0b0	SCTLR_EL2.SED is writeable.
0b1	SCTLR_EL2.SED is not writeable.

ITD	Meaning
0b0	SCTLR_EL2.ITD is writeable.
0b1	SCTLR_EL2.ITD is not writeable.

nAA	Meaning
0b0	SCTLR_EL2.nAA is writeable.
0b1	SCTLR_EL2.nAA is not writeable.

CP15BEN	Meaning
0b0	SCTLR_EL2.CP15BEN is writeable.
0b1	SCTLR_EL2.CP15BEN is not writeable.

SA0	Meaning
0b0	SCTLR_EL2.SA0 is writeable.
0b1	SCTLR_EL2.SA0 is not writeable.

SA	Meaning
0b0	SCTLR_EL2.SA is writeable.
0b1	SCTLR_EL2.SA is not writeable.

C	Meaning
0b0	SCTLR_EL2.C is writeable.
0b1	SCTLR_EL2.C is not writeable.

A	Meaning
0b0	SCTLR_EL2.A is writeable.
0b1	SCTLR_EL2.A is not writeable.

M	Meaning
0b0	SCTLR_EL2.M is writeable.
0b1	SCTLR_EL2.M is not writeable.

SCTLRMASK_EL2, System Control Masking Register (EL2)

Purpose

Configuration

Attributes

Field descriptions

TIDCP, bit [63]When FEAT_TIDCP1 is implemented:

Otherwise:

SPINTMASK, bit [62]When FEAT_NMI is implemented:

Otherwise:

NMI, bit [61]When FEAT_NMI is implemented:

Otherwise:

EnTP2, bit [60]When FEAT_SME is implemented:

Otherwise:

TCSO, bit [59]When FEAT_MTE_STORE_ONLY is implemented:

Otherwise:

TCSO0, bit [58]When FEAT_MTE_STORE_ONLY is implemented:

Otherwise:

EPAN, bit [57]When FEAT_PAN3 is implemented:

Otherwise:

EnALS, bit [56]When FEAT_LS64 is implemented:

Otherwise:

EnAS0, bit [55]When FEAT_LS64_ACCDATA is implemented:

Otherwise:

EnASR, bit [54]When FEAT_LS64_V is implemented:

Otherwise:

TME, bit [53]When FEAT_TME is implemented:

Otherwise:

TME0, bit [52]When FEAT_TME is implemented:

Otherwise:

TMT, bit [51]When FEAT_TME is implemented:

Otherwise:

TMT0, bit [50]When FEAT_TME is implemented:

Otherwise:

Bits [49:47]

TWEDEL, bit [46]When FEAT_TWED is implemented:

Otherwise:

TWEDEn, bit [45]When FEAT_TWED is implemented:

Otherwise:

DSSBS, bit [44]When FEAT_SSBS is implemented:

Otherwise:

ATA, bit [43]When FEAT_MTE2 is implemented:

Otherwise:

ATA0, bit [42]When FEAT_MTE2 is implemented:

Otherwise:

Bit [41]

TCF, bit [40]When FEAT_MTE2 is implemented:

Otherwise:

Bit [39]

TCF0, bit [38]When FEAT_MTE2 is implemented:

Otherwise:

ITFSB, bit [37]When FEAT_MTE_ASYNC is implemented:

Otherwise:

BT, bit [36]When FEAT_BTI is implemented:

Otherwise:

BT0, bit [35]When FEAT_BTI is implemented:

Otherwise:

EnFPM, bit [34]When FEAT_FPMR is implemented:

Otherwise:

MSCEn, bit [33]When FEAT_MOPS is implemented:

Otherwise:

CMOW, bit [32]When FEAT_CMOW is implemented:

Otherwise:

EnIA, bit [31]When FEAT_PAuth is implemented:

Otherwise:

EnIB, bit [30]When FEAT_PAuth is implemented:

Otherwise:

LSMAOE, bit [29]When FEAT_LSMAOC is implemented:

Otherwise:

nTLSMD, bit [28]When FEAT_LSMAOC is implemented:

Otherwise:

EnDA, bit [27]When FEAT_PAuth is implemented:

Otherwise:

UCI, bit [26]

EE, bit [25]When FEAT_MixedEnd is implemented:

Otherwise:

E0E, bit [24]When FEAT_MixedEndEL0 is implemented:

Otherwise:

SPAN, bit [23]

EIS, bit [22]When FEAT_ExS is implemented:

Otherwise:

TIDCP, bit [63]
When FEAT_TIDCP1 is implemented:

SPINTMASK, bit [62]
When FEAT_NMI is implemented:

NMI, bit [61]
When FEAT_NMI is implemented:

EnTP2, bit [60]
When FEAT_SME is implemented:

TCSO, bit [59]
When FEAT_MTE_STORE_ONLY is implemented:

TCSO0, bit [58]
When FEAT_MTE_STORE_ONLY is implemented:

EPAN, bit [57]
When FEAT_PAN3 is implemented:

EnALS, bit [56]
When FEAT_LS64 is implemented:

EnAS0, bit [55]
When FEAT_LS64_ACCDATA is implemented:

EnASR, bit [54]
When FEAT_LS64_V is implemented:

TME, bit [53]
When FEAT_TME is implemented:

TME0, bit [52]
When FEAT_TME is implemented:

TMT, bit [51]
When FEAT_TME is implemented:

TMT0, bit [50]
When FEAT_TME is implemented:

TWEDEL, bit [46]
When FEAT_TWED is implemented:

TWEDEn, bit [45]
When FEAT_TWED is implemented:

DSSBS, bit [44]
When FEAT_SSBS is implemented:

ATA, bit [43]
When FEAT_MTE2 is implemented:

ATA0, bit [42]
When FEAT_MTE2 is implemented:

TCF, bit [40]
When FEAT_MTE2 is implemented:

TCF0, bit [38]
When FEAT_MTE2 is implemented:

ITFSB, bit [37]
When FEAT_MTE_ASYNC is implemented:

BT, bit [36]
When FEAT_BTI is implemented:

BT0, bit [35]
When FEAT_BTI is implemented:

EnFPM, bit [34]
When FEAT_FPMR is implemented:

MSCEn, bit [33]
When FEAT_MOPS is implemented:

CMOW, bit [32]
When FEAT_CMOW is implemented:

EnIA, bit [31]
When FEAT_PAuth is implemented:

EnIB, bit [30]
When FEAT_PAuth is implemented:

LSMAOE, bit [29]
When FEAT_LSMAOC is implemented:

nTLSMD, bit [28]
When FEAT_LSMAOC is implemented:

EnDA, bit [27]
When FEAT_PAuth is implemented:

EE, bit [25]
When FEAT_MixedEnd is implemented:

E0E, bit [24]
When FEAT_MixedEndEL0 is implemented:

EIS, bit [22]
When FEAT_ExS is implemented:

IESB, bit [21]
When FEAT_IESB is implemented:

TSCXT, bit [20]
When FEAT_CSV2_2 is implemented or FEAT_CSV2_1p2 is implemented:

EnDB, bit [13]
When FEAT_PAuth is implemented:

EOS, bit [11]
When FEAT_ExS is implemented:

EnRCTX, bit [10]
When FEAT_SPECRES is implemented:

SED, bit [8]
When EL0 is capable of using AArch32:

ITD, bit [7]
When EL0 is capable of using AArch32:

CP15BEN, bit [5]
When EL0 is capable of using AArch32: