SCTLR2MASK

Mask register to prevent updates of fields in SCTLR2_EL1 on writes to SCTLR2_EL1 or SCTLR2ALIAS_EL1.

Configuration

This register is present only when FEAT_SRMASK is implemented. Otherwise, direct accesses to SCTLR2MASK_EL1 are UNDEFINED.

Attributes

Field descriptions

Bits [63:13]

CPTM0, bit [12]
When FEAT_CPA2 is implemented:

CPTM0	Meaning
0b0	SCTLR2_EL1.CPTM0 is writeable.
0b1	SCTLR2_EL1.CPTM0 is not writeable.

Otherwise:

CPTM, bit [11]
When FEAT_CPA2 is implemented:

CPTM	Meaning
0b0	SCTLR2_EL1.CPTM is writeable.
0b1	SCTLR2_EL1.CPTM is not writeable.

Otherwise:

CPTA0, bit [10]
When FEAT_CPA2 is implemented:

CPTA0	Meaning
0b0	SCTLR2_EL1.CPTA0 is writeable.
0b1	SCTLR2_EL1.CPTA0 is not writeable.

Otherwise:

CPTA, bit [9]
When FEAT_CPA2 is implemented:

CPTA	Meaning
0b0	SCTLR2_EL1.CPTA is writeable.
0b1	SCTLR2_EL1.CPTA is not writeable.

Otherwise:

EnPACM0, bit [8]
When FEAT_PAuth_LR is implemented:

EnPACM0	Meaning
0b0	SCTLR2_EL1.EnPACM0 is writeable.
0b1	SCTLR2_EL1.EnPACM0 is not writeable.

Otherwise:

EnPACM, bit [7]
When FEAT_PAuth_LR is implemented:

EnPACM	Meaning
0b0	SCTLR2_EL1.EnPACM is writeable.
0b1	SCTLR2_EL1.EnPACM is not writeable.

Otherwise:

EnIDCP128, bit [6]
When FEAT_SYSREG128 is implemented:

EnIDCP128	Meaning
0b0	SCTLR2_EL1.EnIDCP128 is writeable.
0b1	SCTLR2_EL1.EnIDCP128 is not writeable.

Otherwise:

EASE, bit [5]
When FEAT_DoubleFault2 is implemented:

EASE	Meaning
0b0	SCTLR2_EL1.EASE is writeable.
0b1	SCTLR2_EL1.EASE is not writeable.

Otherwise:

EnANERR, bit [4]
When FEAT_ANERR is implemented:

EnANERR	Meaning
0b0	SCTLR2_EL1.EnANERR is writeable.
0b1	SCTLR2_EL1.EnANERR is not writeable.

Otherwise:

EnADERR, bit [3]
When FEAT_ADERR is implemented:

EnADERR	Meaning
0b0	SCTLR2_EL1.EnADERR is writeable.
0b1	SCTLR2_EL1.EnADERR is not writeable.

Otherwise:

NMEA, bit [2]
When FEAT_DoubleFault2 is implemented:

NMEA	Meaning
0b0	SCTLR2_EL1.NMEA is writeable.
0b1	SCTLR2_EL1.NMEA is not writeable.

Otherwise:

Bits [1:0]

Accessing SCTLR2MASK_EL1

When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name SCTLR2MASK_EL1 or SCTLR2MASK_EL12 are not guaranteed to be ordered with respect to accesses using the other accessor name.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, SCTLR2MASK_EL1

op0	op1	CRn	CRm	op2
0b11	0b000	0b0001	0b0100	0b011

if !IsFeatureImplemented(FEAT_SRMASK) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3.FGTEn2 == '0') || HFGRTR2_EL2.nSCTLR2MASK_EL1 == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.SRMASKEn == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then X[t, 64] = NVMem[0x328]; else X[t, 64] = SCTLR2MASK_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif ELIsInHost(EL2) then X[t, 64] = SCTLR2MASK_EL2; else X[t, 64] = SCTLR2MASK_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = SCTLR2MASK_EL1;

MSR SCTLR2MASK_EL1, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b000	0b0001	0b0100	0b011

if !IsFeatureImplemented(FEAT_SRMASK) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3.FGTEn2 == '0') || HFGWTR2_EL2.nSCTLR2MASK_EL1 == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.SRMASKEn == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem[0x328] = X[t, 64]; elsif !IsZero(EffectiveSCTLR2MASK_EL1()) then UNDEFINED; else SCTLR2MASK_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif ELIsInHost(EL2) then if !IsZero(EffectiveSCTLR2MASK_EL2()) then UNDEFINED; else SCTLR2MASK_EL2 = X[t, 64]; else SCTLR2MASK_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then SCTLR2MASK_EL1 = X[t, 64];

MRS <Xt>, SCTLR2MASK_EL12

op0	op1	CRn	CRm	op2
0b11	0b101	0b0001	0b0100	0b011

if !IsFeatureImplemented(FEAT_SRMASK) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X[t, 64] = NVMem[0x328]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = SCTLR2MASK_EL1; else UNDEFINED; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X[t, 64] = SCTLR2MASK_EL1; else UNDEFINED;

MSR SCTLR2MASK_EL12, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b101	0b0001	0b0100	0b011

if !IsFeatureImplemented(FEAT_SRMASK) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem[0x328] = X[t, 64]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else SCTLR2MASK_EL1 = X[t, 64]; else UNDEFINED; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then SCTLR2MASK_EL1 = X[t, 64]; else UNDEFINED;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0																			CPTM0	CPTM	CPTA0	CPTA	EnPACM0	EnPACM	EnIDCP128	EASE	EnANERR	EnADERR	NMEA	RES0

SCTLR2MASK_EL1, Extended System Control Masking Register (EL1)

Purpose

Configuration

Attributes

Field descriptions

Bits [63:13]

CPTM0, bit [12]
When FEAT_CPA2 is implemented:

Otherwise:

CPTM, bit [11]
When FEAT_CPA2 is implemented:

Otherwise:

CPTA0, bit [10]
When FEAT_CPA2 is implemented:

Otherwise:

CPTA, bit [9]
When FEAT_CPA2 is implemented:

Otherwise:

EnPACM0, bit [8]
When FEAT_PAuth_LR is implemented:

Otherwise:

EnPACM, bit [7]
When FEAT_PAuth_LR is implemented:

Otherwise:

EnIDCP128, bit [6]
When FEAT_SYSREG128 is implemented:

Otherwise:

EASE, bit [5]
When FEAT_DoubleFault2 is implemented:

Otherwise:

EnANERR, bit [4]
When FEAT_ANERR is implemented:

Otherwise:

EnADERR, bit [3]
When FEAT_ADERR is implemented:

Otherwise:

NMEA, bit [2]
When FEAT_DoubleFault2 is implemented:

Otherwise:

Bits [1:0]

Accessing SCTLR2MASK_EL1

MRS <Xt>, SCTLR2MASK_EL1

MSR SCTLR2MASK_EL1, <Xt>

MRS <Xt>, SCTLR2MASK_EL12

MSR SCTLR2MASK_EL12, <Xt>

SCTLR2MASK_EL1, Extended System Control Masking Register (EL1)

Purpose

Configuration

Attributes

Field descriptions

Bits [63:13]

CPTM0, bit [12]When FEAT_CPA2 is implemented:

Otherwise:

CPTM, bit [11]When FEAT_CPA2 is implemented:

Otherwise:

CPTA0, bit [10]When FEAT_CPA2 is implemented:

Otherwise:

CPTA, bit [9]When FEAT_CPA2 is implemented:

Otherwise:

EnPACM0, bit [8]When FEAT_PAuth_LR is implemented:

Otherwise:

EnPACM, bit [7]When FEAT_PAuth_LR is implemented:

Otherwise:

EnIDCP128, bit [6]When FEAT_SYSREG128 is implemented:

Otherwise:

EASE, bit [5]When FEAT_DoubleFault2 is implemented:

Otherwise:

EnANERR, bit [4]When FEAT_ANERR is implemented:

Otherwise:

EnADERR, bit [3]When FEAT_ADERR is implemented:

Otherwise:

NMEA, bit [2]When FEAT_DoubleFault2 is implemented:

Otherwise:

Bits [1:0]

Accessing SCTLR2MASK_EL1

MRS <Xt>, SCTLR2MASK_EL1

MSR SCTLR2MASK_EL1, <Xt>

MRS <Xt>, SCTLR2MASK_EL12

MSR SCTLR2MASK_EL12, <Xt>

CPTM0, bit [12]
When FEAT_CPA2 is implemented:

CPTM, bit [11]
When FEAT_CPA2 is implemented:

CPTA0, bit [10]
When FEAT_CPA2 is implemented:

CPTA, bit [9]
When FEAT_CPA2 is implemented:

EnPACM0, bit [8]
When FEAT_PAuth_LR is implemented:

EnPACM, bit [7]
When FEAT_PAuth_LR is implemented:

EnIDCP128, bit [6]
When FEAT_SYSREG128 is implemented:

EASE, bit [5]
When FEAT_DoubleFault2 is implemented:

EnANERR, bit [4]
When FEAT_ANERR is implemented:

EnADERR, bit [3]
When FEAT_ADERR is implemented:

NMEA, bit [2]
When FEAT_DoubleFault2 is implemented: