The PMBMAR_EL1 characteristics are:
Controls Statistical Profiling Unit accesses to memory.
If the Profiling Buffer pointers specify virtual addresses, the address properties are defined by the translation tables and this register is ignored.
This register is present only when FEAT_SPE_nVM is implemented. Otherwise, direct accesses to PMBMAR_EL1 are UNDEFINED.
PMBMAR_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | SH | Attr | |||||||||||||||||||||||||||||
Reserved, RES0.
Profiling Buffer shareability domain. Defines the shareability domain for Normal memory used by the Profiling Buffer.
| SH | Meaning |
|---|---|
| 0b00 |
Non-shareable. |
| 0b10 |
Outer Shareable. |
| 0b11 |
Inner Shareable. |
All other values are reserved.
This field is ignored when PMBMAR_EL1.Attr specifies any of the following memory types:
All Device and Normal Inner Non-cacheable Outer Non-cacheable memory regions are always treated as Outer Shareable.
The reset behavior of this field is:
Profiling Buffer memory type and attributes. Defines the memory type and, for Normal memory, the cacheability attributes, for memory addressed by the Profiling Buffer.
The encoding of this field is the same as that of a MAIR_ELx.Attr<n> field, as follows:
| Attr | Meaning | |
|---|---|---|
| 0b0000dd00 | Device memory. See encoding of 'dd' for the type of Device memory. | |
| 0b0000dd01 | If FEAT_XS is implemented: Device memory with the XS attribute set to 0. See encoding of 'dd' for the type of Device memory. Otherwise,UNPREDICTABLE. | |
| 0b0000dd1x | UNPREDICTABLE. | |
| 0booooiiii | where oooo != 0000 and iiii != 0000 | Normal memory. See encoding of 'oooo' and 'iiii' for the type of Normal memory. |
| 0b01000000 | If FEAT_XS is implemented: Normal Inner Non-cacheable, Outer Non-cacheable memory with the XS attribute set to 0. Otherwise,UNPREDICTABLE. | |
| 0b10100000 | If FEAT_XS is implemented: Normal Inner Write-through Cacheable, Outer Write-through Cacheable, Read-Allocate, No-Write Allocate, Non-transient memory with the XS attribute set to 0. Otherwise,UNPREDICTABLE. | |
| 0b11110000 | If FEAT_MTE2 is implemented: Tagged Normal Inner Write-Back, Outer Write-Back, Read-Allocate, Write-Allocate Non-transient memory. Otherwise,UNPREDICTABLE. | |
| 0bxxxx0000 | where xxxx != 0000 and xxxx != 0100 and xxxx != 1010 and xxxx != 1111 | UNPREDICTABLE. |
dd is encoded as follows:
| 'dd' | Meaning |
|---|---|
| 0b00 | Device-nGnRnE memory. |
| 0b01 | Device-nGnRE memory. |
| 0b10 | Device-nGRE memory. |
| 0b11 | Device-GRE memory. |
oooo is encoded as follows:
| 'oooo' | Meaning | |
|---|---|---|
| 0b0000 | See encoding of Attr. | |
| 0b00RW | where RW != 00 | Normal memory, Outer Write-Through Transient. |
| 0b0100 | Normal memory, Outer Non-cacheable. | |
| 0b01RW | where RW != 00 | Normal memory, Outer Write-Back Transient. |
| 0b10RW | Normal memory, Outer Write-Through Non-transient. | |
| 0b11RW | Normal memory, Outer Write-Back Non-transient. |
R encodes the Outer Read-Allocate policy and W encodes the Outer Write-Allocate policy.
iiii is encoded as follows:
| 'iiii' | Meaning | |
|---|---|---|
| 0b0000 | See encoding of Attr. | |
| 0b00RW | where RW != 00 | Normal memory, Inner Write-Through Transient. |
| 0b0100 | Normal memory, Inner Non-cacheable. | |
| 0b01RW | where RW != 00 | Normal memory, Inner Write-Back Transient. |
| 0b10RW | Normal memory, Inner Write-Through Non-transient. | |
| 0b11RW | Normal memory, Inner Write-Back Non-transient. |
R encodes the Inner Read-Allocate policy and W encodes the Inner Write-Allocate policy.
In oooo and iiii, R and W are encoded as follows:
| 'R' or 'W' | Meaning |
|---|---|
| 0b0 | No Allocate. |
| 0b1 | Allocate. |
When FEAT_XS is implemented, stage 1 Inner Write-Back Cacheable, Outer Write-Back Cacheable memory types have the XS attribute set to 0.
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1001 | 0b1010 | 0b101 |
if !IsFeatureImplemented(FEAT_SPE_nVM) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.EnPMS4 == '0' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3.FGTEn2 == '0') || HDFGRTR2_EL2.nPMBMAR_EL1 == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.E2PB IN {'x0'} then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.EnPMS4 == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMBMAR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.EnPMS4 == '0' then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.EnPMS4 == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMBMAR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = PMBMAR_EL1;
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1001 | 0b1010 | 0b101 |
if !IsFeatureImplemented(FEAT_SPE_nVM) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.EnPMS4 == '0' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3.FGTEn2 == '0') || HDFGWTR2_EL2.nPMBMAR_EL1 == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.E2PB IN {'x0'} then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.EnPMS4 == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMBMAR_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.EnPMS4 == '0' then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.EnPMS4 == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMBMAR_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then PMBMAR_EL1 = X[t, 64];
15/12/2024 22:27; 5e0a212688c6bd7aee92394b6f5e491b4d0fee1d
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