PMBIDR

Provides information to software as to whether the buffer can be programmed at the current Exception level.

Configuration

This register is present only when FEAT_SPE is implemented. Otherwise, direct accesses to PMBIDR_EL1 are UNDEFINED.

Attributes

Field descriptions

Bits [63:48]

MaxBuffSize, bits [47:32]

Maximum supported Profiling Buffer size. Reserved for software use.

The only permitted value is 0x0000, indicating there is no limit to the maximum buffer size.

Note

Permitted values relate to the values an implementation is permitted to set this field to. A hypervisor might trap accesses to this register and use other defined values to describe limitations of its virtualization support to a Guest operating system, as follows:

MaxBuffSize bits[8:0] indicate a mantissa value, M.
MaxBuffSize bits[13:9] indicate an exponent value, E.
MaxBuffSize bits[15:14] are reserved.

The maximum buffer size, in bytes, is expressed using the following function:

if IsZero(E) then UInt(M:Zeros(12)) else UInt('1':M:Zeros(UInt(E)+11))

For example:

A value of 0x0001 indicates a maximum buffer size of 4KB.
A value of 0x3FFF indicates a maximum buffer size of 4092TB.

Reads as 0x0000.

Access to this field is RO.

Bits [31:12]

EA, bits [11:8]

External Abort handling. Describes how the PE manages External aborts on writes made by the Statistical Profiling Unit to the Profiling Buffer.

The value of this field is an IMPLEMENTATION DEFINED choice of:

EA	Meaning
0b0000	Not described.
0b0001	The PE ignores External aborts on writes made by the Statistical Profiling Unit.
0b0010	An External abort on a write made by the Statistical Profiling Unit generates an asynchronous SError exception at the PE.

All other values are reserved.

From Armv8.8, the value 0b0000 is not permitted.

PMBIDR_EL1.EA describes only External aborts generated by the write to memory. External aborts on a translation table walk made by the Statistical Profiling Unit generate Profiling Buffer management events reported as MMU faults using PMBSR_ELx.

Access to this field is RO.

AddrMode, bits [7:6]
When FEAT_SPE_nVM is implemented:

Address Modes. Describes the addressing modes available for the Profiling Buffer.

AddrMode	Meaning
0b00	Only virtual address mode is supported.
0b01	Virtual and physical address modes are supported.
0b11	Reserved for software use under virtualization, to indicate that only physical address mode is supported.

Other values are reserved.

If the Effective value of PMSCR_EL2.EnVM is 1 and the value returned for PMBIDR_EL1.P is 0, then this field reads as 0b01. Otherwise, this field reads as 0b00.

Note

A hypervisor might trap accesses to this register to describe limitations of its virtualization support to a Guest operating system.

Otherwise:

F, bit [5]

Flag updates. Describes how address translations performed by the Statistical Profiling Unit manage the Access flag and dirty state.

The value of this field is an IMPLEMENTATION DEFINED choice of:

F	Meaning
0b0	Hardware management of the Access flag and dirty state for accesses made by the Statistical Profiling Unit is always disabled for all translation stages.
0b1	Hardware management of the Access flag and dirty state for accesses made by the Statistical Profiling Unit is controlled in the same way as explicit memory accesses in the Profiling Buffer owning translation regime.

Note

If hardware management of the Access flag is disabled for a stage of translation, an access to a Page or Block with the Access flag bit not set in the descriptor will generate an Access Flag fault.

If hardware management of the dirty state is disabled for a stage of translation, an access to a Page or Block will ignore the Dirty Bit Modifier in the descriptor and might generate a Permission fault, depending on the values of the access permission bits in the descriptor.

From Armv8.8, the value 0 is not permitted.

Access to this field is RO.

P, bit [4]

Programming not allowed. When read at EL3, this field reads as zero. Otherwise, indicates that the Profiling Buffer is owned by a higher Exception level or another Security state.

P	Meaning
0b0	Programming is allowed.
0b1	Programming not allowed.

The value read from this field depends on the current Exception level and the Effective values of MDCR_EL3.NSPB, MDCR_EL3.NSPBE, and MDCR_EL2.E2PB:

If EL3 is implemented, MDCR_EL3.NSPB is 0b0x, and either FEAT_RME is not implemented, or Secure state is implemented and MDCR_EL3.NSPBE is 0, then this field reads as one from:
- Non-secure EL1 and Non-secure EL2.
- If FEAT_RME is implemented, Realm EL1 and Realm EL2.
- If Secure EL2 is implemented and enabled, and MDCR_EL2.E2PB is 0b00, Secure EL1.
If EL3 is implemented, MDCR_EL3.NSPB is 0b1x and either FEAT_RME is not implemented or MDCR_EL3.NSPBE is 0, then this field reads as one from:
- If Secure state is implemented, Secure EL1.
- If Secure EL2 is implemented, Secure EL2.
- If EL2 is implemented and MDCR_EL2.E2PB is 0b00, Non-secure EL1.
- If FEAT_RME is implemented, Realm EL1 and Realm EL2.
If FEAT_RME is implemented, and MDCR_EL3.{NSPB, NSPBE} is {0b1x, 1}, then this field reads as one from:
- Non-secure EL1 and Non-secure EL2.
- If Secure state is implemented, Secure EL1 and Secure EL2.
- If MDCR_EL2.E2PB is 0b00, Realm EL1.
If EL3 is not implemented, EL2 is implemented, and MDCR_EL2.E2PB is 0b00, then this field reads as one from EL1.

Otherwise, this field reads as zero.

Align, bits [3:0]

Defines the minimum alignment constraint for writes to PMBPTR_EL1.

The value of this field is an IMPLEMENTATION DEFINED choice of:

Align	Meaning
0b0000	Byte.
0b0001	Halfword.
0b0010	Word.
0b0011	Doubleword.
0b0100	16 bytes.
0b0101	32 bytes.
0b0110	64 bytes.
0b0111	128 bytes.
0b1000	256 bytes.
0b1001	512 bytes.
0b1010	1KB.
0b1011	2KB.

All other values are reserved.

For more information, see 'Restrictions on the current write pointer'.

If this field is nonzero, then every record is a multiple of this size.

Access to this field is RO.

Accessing PMBIDR_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PMBIDR_EL1

op0	op1	CRn	CRm	op2
0b11	0b000	0b1001	0b1010	0b111

if !IsFeatureImplemented(FEAT_SPE) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMBIDR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = PMBIDR_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = PMBIDR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = PMBIDR_EL1;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																MaxBuffSize
RES0																				EA				AddrMode		F	P	Align

PMBIDR_EL1, Profiling Buffer ID Register

Purpose

Configuration

Attributes

Field descriptions

Bits [63:48]

MaxBuffSize, bits [47:32]

Bits [31:12]

EA, bits [11:8]

AddrMode, bits [7:6]
When FEAT_SPE_nVM is implemented:

Otherwise:

F, bit [5]

P, bit [4]

Align, bits [3:0]

Accessing PMBIDR_EL1

MRS <Xt>, PMBIDR_EL1

PMBIDR_EL1, Profiling Buffer ID Register

Purpose

Configuration

Attributes

Field descriptions

Bits [63:48]

MaxBuffSize, bits [47:32]

Bits [31:12]

EA, bits [11:8]

AddrMode, bits [7:6]When FEAT_SPE_nVM is implemented:

Otherwise:

F, bit [5]

P, bit [4]

Align, bits [3:0]

Accessing PMBIDR_EL1

MRS <Xt>, PMBIDR_EL1

AddrMode, bits [7:6]
When FEAT_SPE_nVM is implemented: