The ID_AA64FPFR0_EL1 characteristics are:
Provides information about the FP8 formats and instructions implemented in AArch64 state.
The fields in this register do not follow the standard ID scheme. See Alternative ID scheme used for ID_AA64SMFR0_EL1 and ID_AA64FPFR0_EL1.
Prior to the introduction of the features described by this register, this register was unnamed and reserved, RES0 from EL1, EL2, and EL3.
ID_AA64FPFR0_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| F8CVT | F8FMA | F8DP4 | F8DP2 | F8MM8 | F8MM4 | RES0 | RAZ | F8E4M3 | F8E5M2 | ||||||||||||||||||||||
Reserved, RES0.
Indicates support for the following instructions:
The Advanced SIMD floating-point scaling instruction FSCALE.
The Advanced SIMD FP8 convert instructions BF1CVTL, BF1CVTL2, BF2CVTL, BF2CVTL2, F1CVTL, F1CVTL2, F2CVTL, F2CVTL2, FCVTN, and FCVTN2.
When FEAT_SVE2 or FEAT_SME2 is implemented, the SVE2 FP8 convert instructions BF1CVT, BF1CVTLT, BF2CVT, BF2CVTLT, F1CVT, F1CVTLT, F2CVT, F2CVTLT, BFCVTN, FCVTN, FCVTNB, and FCVTNT.
When FEAT_SME2 is implemented, the SME2 multi-vector floating-point scaling instruction FSCALE and the SME2 FP8 convert instructions BF1CVT, BF1CVTL, BF2CVT, BF2CVTL, F1CVT, F1CVTL, F2CVT, F2CVTL, BFCVT, FCVT, and FCVTN.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| F8CVT | Meaning |
|---|---|
| 0b0 |
The specified instructions are not implemented. |
| 0b1 |
The specified instructions are implemented. |
FEAT_FP8 implements the functionality identified by the value 1.
Access to this field is RO.
Indicates support for the following instructions:
The value of this field is an IMPLEMENTATION DEFINED choice of:
| F8FMA | Meaning |
|---|---|
| 0b0 |
The specified instructions are not implemented. |
| 0b1 |
The specified instructions are implemented. |
FEAT_FP8FMA implements the functionality identified by the value 1.
Access to this field is RO.
Indicates support for the following instructions:
The value of this field is an IMPLEMENTATION DEFINED choice of:
| F8DP4 | Meaning |
|---|---|
| 0b0 |
The specified instructions are not implemented by this feature. |
| 0b1 |
The specified instructions are implemented. |
Other features may implement some of the specified instructions.
All other values are reserved.
FEAT_FP8DOT4 implements the functionality identified by the value 1.
Access to this field is RO.
Indicates support for the following instructions:
The value of this field is an IMPLEMENTATION DEFINED choice of:
| F8DP2 | Meaning |
|---|---|
| 0b0 |
The specified instructions are not implemented by this feature. |
| 0b1 |
The specified instructions are implemented. |
Other features may implement some of the specified instructions.
FEAT_FP8DOT2 implements the functionality identified by the value 1.
Access to this field is RO.
Indicates support for the following instructions:
Advanced SIMD FP8 to single-precision matrix multiply FMMLA (8-way, FP8 to FP32) instruction.
If FEAT_SVE2 is implemented, SVE FP8 to single-precision matrix multiply FMMLA (widening, FP8 to FP32) instruction is implemented when the PE is not in Streaming SVE mode.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| F8MM8 | Meaning |
|---|---|
| 0b0 |
Advanced SIMD and SVE FP8 to single-precision matrix multiply instructions are not implemented by this feature. |
| 0b1 |
The specified Advanced SIMD and SVE FP8 to single-precision matrix multiply instructions are implemented. |
FEAT_F8F32MM implements the functionality identified by the value 0b0001
Access to this field is RO.
Indicates support for the following instructions:
Advanced SIMD FP8 to half-precision matrix multiply FMMLA (4-way, FP8 to FP16) instruction.
If FEAT_SVE2 is implemented, SVE FP8 to half-precision matrix multiply FMMLA (widening, FP8 to FP16) instruction is implemented when the PE is not in Streaming SVE mode.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| F8MM4 | Meaning |
|---|---|
| 0b0 |
Advanced SIMD and SVE FP8 to half-precision matrix multiply instructions are not implemented by this feature. |
| 0b1 |
The specified Advanced SIMD and SVE FP8 to half-precision matrix multiply instructions are implemented. |
FEAT_F8F16MM implements the functionality identified by the value 0b0001
Access to this field is RO.
Reserved, RES0.
Reserved for data formats 2 to 7.
Reserved, RAZ.
Indicates support for OFP8 E4M3 format and behavior for FP8 instructions.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| F8E4M3 | Meaning |
|---|---|
| 0b0 |
OFP8 E4M3 format is not supported. |
| 0b1 |
OFP8 E4M3 format is supported. |
If FEAT_FP8 is implemented, the only permitted value is 1.
Otherwise, the only permitted value is 0.
For more information on OFP8 formats, see the Open Compute Project, OCP 8-bit Floating Point Specification (OFP8).
Access to this field is RO.
Indicates support for OFP8 E5M2 format and behavior for FP8 instructions.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| F8E5M2 | Meaning |
|---|---|
| 0b0 |
OFP8 E5M2 format is not supported. |
| 0b1 |
OFP8 E5M2 format is supported. |
If FEAT_FP8 is implemented, the only permitted value is 1.
Otherwise, the only permitted value is 0.
For more information on OFP8 formats, see the Open Compute Project, OCP 8-bit Floating Point Specification (OFP8).
Access to this field is RO.
Accesses to this register use the following encodings in the System register encoding space:
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b0000 | 0b0100 | 0b111 |
if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3.TID3 == '1' then UNDEFINED; elsif EL2Enabled() && (IsFeatureImplemented(FEAT_FGT) || !IsZero(ID_AA64FPFR0_EL1) || boolean IMPLEMENTATION_DEFINED "ID_AA64FPFR0_EL1 trapped by HCR_EL2.TID3") && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3.TID3 == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = ID_AA64FPFR0_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3.TID3 == '1' then UNDEFINED; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3.TID3 == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = ID_AA64FPFR0_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = ID_AA64FPFR0_EL1;
15/12/2024 22:27; 5e0a212688c6bd7aee92394b6f5e491b4d0fee1d
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