The ID_AA64DFR2_EL1 characteristics are:
Provides top-level information about the debug system in AArch64.
For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'.
Prior to the introduction of the features described by this register, this register was unnamed and reserved, RES0 from EL1, EL2, and EL3.
ID_AA64DFR2_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | TRBE_EXC | SPE_nVM | SPE_EXC | RES0 | BWE | STEP | |||||||||||||||||||||||||
Reserved, RES0.
TRBE Profiling exception extension. Describes support for reporting trace buffer management events as TRBE Profiling exceptions.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| TRBE_EXC | Meaning |
|---|---|
| 0b0000 |
TRBE Profiling exception not implemented. |
| 0b0001 |
TRBE Profiling exception implemented. |
All other values are reserved.
FEAT_TRBE_EXC implements the functionality identified by the value 0b0001.
Access to this field is RO.
Profiling Buffer physical address mode supported. Describes support for defining the Profiling Buffer using physical addresses or intermediate physical addresses.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| SPE_nVM | Meaning |
|---|---|
| 0b0000 |
Profiling Buffer physical address mode not implemented. |
| 0b0001 |
Profiling Buffer physical address mode implemented. |
All other values are reserved.
FEAT_SPE_nVM implements the functionality identified by the value 0b0001.
Access to this field is RO.
SPE Profiling exception extension. Describes support for reporting Profiling Buffer management events as SPE Profiling exceptions.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| SPE_EXC | Meaning |
|---|---|
| 0b0000 |
SPE Profiling exception not implemented. |
| 0b0001 |
SPE Profiling exception implemented. |
All other values are reserved.
FEAT_SPE_EXC implements the functionality identified by the value 0b0001.
Access to this field is RO.
Reserved, RES0.
Breakpoints and watchpoint enhancements.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| BWE | Meaning |
|---|---|
| 0b0000 |
This field does not indicate whether DBGBCR<n>_EL1.MASK and address mismatch breakpoints are implemented. |
| 0b0001 |
DBGBCR<n>_EL1.MASK and address mismatch breakpoints are implemented. |
| 0b0010 |
As 0b0001, and address mismatch watchpoints are implemented. |
All other values are reserved.
FEAT_BWE implements the functionality identified by the value 0b0001.
FEAT_BWE2 implements the functionality identified by the value 0b0010.
When this field is 0b0000, ID_AA64DFR1_EL1.ABLE might indicate the presence of support for DBGBCR<n>_EL1.MASK and address mismatch breakpoints.
From Armv9.5, the value 0b0001 is not permitted.
Access to this field is RO.
Enhanced Software Step Extension.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| STEP | Meaning |
|---|---|
| 0b0000 |
Execution from MDSTEPOP_EL1 is not supported for Software Step. |
| 0b0001 |
Execution from MDSTEPOP_EL1 is supported for Software Step. |
All other values are reserved.
FEAT_STEP2 implements the functionality identified by the value 0b0001.
Access to this field is RO.
Accesses to this register use the following encodings in the System register encoding space:
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b0000 | 0b0101 | 0b010 |
if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3.TID3 == '1' then UNDEFINED; elsif EL2Enabled() && (IsFeatureImplemented(FEAT_FGT) || !IsZero(ID_AA64DFR2_EL1) || boolean IMPLEMENTATION_DEFINED "ID_AA64DFR2_EL1 trapped by HCR_EL2.TID3") && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3.TID3 == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = ID_AA64DFR2_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3.TID3 == '1' then UNDEFINED; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3.TID3 == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = ID_AA64DFR2_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = ID_AA64DFR2_EL1;
15/12/2024 22:27; 5e0a212688c6bd7aee92394b6f5e491b4d0fee1d
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