HFGITR2

This register is present only when FEAT_FGT2 is implemented. Otherwise, direct accesses to HFGITR2_EL2 are UNDEFINED.

Attributes

Field descriptions

Bits [63:2]

nDCCIVAPS, bit [1]
When FEAT_PoPS is implemented:

Trap execution of any of the following AArch64 instructions at EL1 to EL2:

DC CIVAPS.
DC CIGDVAPS, if FEAT_MTE2 is implemented.

If the Point of Physical Storage is before any level of data cache, it is IMPLEMENTATION DEFINED whether the execution of the affected instruction is trapped when the value of this control is 1.

nDCCIVAPS	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then execution at EL1 using AArch64 of any of the specified instructions is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.
0b1	Execution of the specified instructions is not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

TSBCSYNC, bit [0]
When FEAT_TRBEv1p1 is implemented:

Trap execution of TSB CSYNC at EL1 and EL0 using AArch64 to EL2.

TSBCSYNC	Meaning
0b0	Execution of TSB CSYNC is not trapped by this mechanism.
0b1	If EL2 is implemented and enabled in the current Security state, and the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, then execution of TSB CSYNC at EL1 and EL0 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x0A, unless the instruction generates a higher priority exception.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

Accessing HFGITR2_EL2

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, HFGITR2_EL2

op0	op1	CRn	CRm	op2
0b11	0b100	0b0011	0b0001	0b111

if !IsFeatureImplemented(FEAT_FGT2) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X[t, 64] = NVMem[0x310]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.FGTEn2 == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.FGTEn2 == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = HFGITR2_EL2; elsif PSTATE.EL == EL3 then X[t, 64] = HFGITR2_EL2;

MSR HFGITR2_EL2, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b100	0b0011	0b0001	0b111

if !IsFeatureImplemented(FEAT_FGT2) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem[0x310] = X[t, 64]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.FGTEn2 == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.FGTEn2 == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else HFGITR2_EL2 = X[t, 64]; elsif PSTATE.EL == EL3 then HFGITR2_EL2 = X[t, 64];

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0																														nDCCIVAPS	TSBCSYNC

HFGITR2_EL2, Hypervisor Fine-Grained Instruction Trap Register 2

Purpose

Configuration

Attributes

Field descriptions

Bits [63:2]

nDCCIVAPS, bit [1]
When FEAT_PoPS is implemented:

Otherwise:

TSBCSYNC, bit [0]
When FEAT_TRBEv1p1 is implemented:

Otherwise:

Accessing HFGITR2_EL2

MRS <Xt>, HFGITR2_EL2

MSR HFGITR2_EL2, <Xt>

HFGITR2_EL2, Hypervisor Fine-Grained Instruction Trap Register 2

Purpose

Configuration

Attributes

Field descriptions

Bits [63:2]

nDCCIVAPS, bit [1]When FEAT_PoPS is implemented:

Otherwise:

TSBCSYNC, bit [0]When FEAT_TRBEv1p1 is implemented:

Otherwise:

Accessing HFGITR2_EL2

MRS <Xt>, HFGITR2_EL2

MSR HFGITR2_EL2, <Xt>

nDCCIVAPS, bit [1]
When FEAT_PoPS is implemented:

TSBCSYNC, bit [0]
When FEAT_TRBEv1p1 is implemented: