CPTRMASK

This register is present only when FEAT_SRMASK is implemented. Otherwise, direct accesses to CPTRMASK_EL2 are UNDEFINED.

This register has no effect if EL2 is not enabled in the current Security state.

Attributes

Field descriptions

When ELIsInHost(EL2):

Bits [63:32]

TCPAC, bit [31]

TCPAC	Meaning
0b0	CPTR_EL2.TCPAC is writeable.
0b1	CPTR_EL2.TCPAC is not writeable.

TAM, bit [30]
When FEAT_AMUv1 is implemented:

TAM	Meaning
0b0	CPTR_EL2.TAM is writeable.
0b1	CPTR_EL2.TAM is not writeable.

Otherwise:

E0POE, bit [29]
When FEAT_S1POE is implemented:

E0POE	Meaning
0b0	CPTR_EL2.E0POE is writeable.
0b1	CPTR_EL2.E0POE is not writeable.

Otherwise:

TTA, bit [28]
When System register access to the trace unit registers is implemented:

TTA	Meaning
0b0	CPTR_EL2.TTA is writeable.
0b1	CPTR_EL2.TTA is not writeable.

Otherwise:

Bits [27:25]

SMEN, bit [24]
When FEAT_SME is implemented:

SMEN	Meaning
0b0	CPTR_EL2.SMEN is writeable.
0b1	CPTR_EL2.SMEN is not writeable.

Otherwise:

Bits [23:21]

FPEN, bit [20]

Bits [19:17]

FPEN	Meaning
0b0	CPTR_EL2.FPEN is writeable.
0b1	CPTR_EL2.FPEN is not writeable.

ZEN, bit [16]
When FEAT_SVE is implemented:

ZEN	Meaning
0b0	CPTR_EL2.ZEN is writeable.
0b1	CPTR_EL2.ZEN is not writeable.

Otherwise:

Bits [15:0]

Otherwise:

Bits [63:32]

TCPAC, bit [31]

TCPAC	Meaning
0b0	CPTR_EL2.TCPAC is writeable.
0b1	CPTR_EL2.TCPAC is not writeable.

TAM, bit [30]
When FEAT_AMUv1 is implemented:

TAM	Meaning
0b0	CPTR_EL2.TAM is writeable.
0b1	CPTR_EL2.TAM is not writeable.

Otherwise:

Bits [29:21]

TTA, bit [20]

Bits [19:13]

TTA	Meaning
0b0	CPTR_EL2.TTA is writeable.
0b1	CPTR_EL2.TTA is not writeable.

TSM, bit [12]
When FEAT_SME is implemented:

TSM	Meaning
0b0	CPTR_EL2.TSM is writeable.
0b1	CPTR_EL2.TSM is not writeable.

Otherwise:

Bit [11]

TFP, bit [10]

Bit [9]

TFP	Meaning
0b0	CPTR_EL2.TFP is writeable.
0b1	CPTR_EL2.TFP is not writeable.

TZ, bit [8]
When FEAT_SVE is implemented:

TZ	Meaning
0b0	CPTR_EL2.TZ is writeable.
0b1	CPTR_EL2.TZ is not writeable.

Otherwise:

Bits [7:0]

Accessing CPTRMASK_EL2

When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL2 using the accessor name CPTRMASK_EL2 or CPTRMASK_EL1 are not guaranteed to be ordered with respect to accesses using the other accessor name.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, CPTRMASK_EL2

op0	op1	CRn	CRm	op2
0b11	0b100	0b0001	0b0100	0b010

if !IsFeatureImplemented(FEAT_SRMASK) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = CPTRMASK_EL2; elsif PSTATE.EL == EL3 then X[t, 64] = CPTRMASK_EL2;

MSR CPTRMASK_EL2, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b100	0b0001	0b0100	0b010

if !IsFeatureImplemented(FEAT_SRMASK) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif !IsZero(EffectiveCPTRMASK_EL2()) then UNDEFINED; else CPTRMASK_EL2 = X[t, 64]; elsif PSTATE.EL == EL3 then CPTRMASK_EL2 = X[t, 64];

MRS <Xt>, CPACRMASK_EL1

op0	op1	CRn	CRm	op2
0b11	0b000	0b0001	0b0100	0b010

if !IsFeatureImplemented(FEAT_SRMASK) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3.FGTEn2 == '0') || HFGRTR2_EL2.nCPACRMASK_EL1 == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.SRMASKEn == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then X[t, 64] = NVMem[0x320]; else X[t, 64] = CPACRMASK_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif ELIsInHost(EL2) then X[t, 64] = CPTRMASK_EL2; else X[t, 64] = CPACRMASK_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = CPACRMASK_EL1;

MSR CPACRMASK_EL1, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b000	0b0001	0b0100	0b010

if !IsFeatureImplemented(FEAT_SRMASK) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3.FGTEn2 == '0') || HFGWTR2_EL2.nCPACRMASK_EL1 == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.SRMASKEn == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem[0x320] = X[t, 64]; elsif !IsZero(EffectiveCPACRMASK_EL1()) then UNDEFINED; else CPACRMASK_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif ELIsInHost(EL2) then if !IsZero(EffectiveCPTRMASK_EL2()) then UNDEFINED; else CPTRMASK_EL2 = X[t, 64]; else CPACRMASK_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then CPACRMASK_EL1 = X[t, 64];

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
TCPAC	TAM	E0POE	TTA	RES0			SMEN	RES0			FPEN	RES0			ZEN	RES0

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
TCPAC	TAM	RES0									TTA	RES0							TSM	RES0	TFP	RES0	TZ	RES0

CPTRMASK_EL2, Architectural Feature Trap Masking Register

Purpose

Configuration

Attributes

Field descriptions

When ELIsInHost(EL2):

Bits [63:32]

TCPAC, bit [31]

TAM, bit [30]When FEAT_AMUv1 is implemented:

Otherwise:

E0POE, bit [29]When FEAT_S1POE is implemented:

Otherwise:

TTA, bit [28]When System register access to the trace unit registers is implemented:

Otherwise:

Bits [27:25]

SMEN, bit [24]When FEAT_SME is implemented:

Otherwise:

Bits [23:21]

FPEN, bit [20]

Bits [19:17]

ZEN, bit [16]When FEAT_SVE is implemented:

Otherwise:

Bits [15:0]

Otherwise:

Bits [63:32]

TCPAC, bit [31]

TAM, bit [30]When FEAT_AMUv1 is implemented:

Otherwise:

Bits [29:21]

TTA, bit [20]

Bits [19:13]

TSM, bit [12]When FEAT_SME is implemented:

Otherwise:

Bit [11]

TFP, bit [10]

Bit [9]

TZ, bit [8]When FEAT_SVE is implemented:

Otherwise:

Bits [7:0]

Accessing CPTRMASK_EL2

MRS <Xt>, CPTRMASK_EL2

MSR CPTRMASK_EL2, <Xt>

MRS <Xt>, CPACRMASK_EL1

MSR CPACRMASK_EL1, <Xt>

TAM, bit [30]
When FEAT_AMUv1 is implemented:

E0POE, bit [29]
When FEAT_S1POE is implemented:

TTA, bit [28]
When System register access to the trace unit registers is implemented:

SMEN, bit [24]
When FEAT_SME is implemented:

ZEN, bit [16]
When FEAT_SVE is implemented:

TAM, bit [30]
When FEAT_AMUv1 is implemented:

TSM, bit [12]
When FEAT_SME is implemented:

TZ, bit [8]
When FEAT_SVE is implemented: