ACTLR_EL1, Auxiliary Control Register (EL1)

The ACTLR_EL1 characteristics are:

Purpose

Provides IMPLEMENTATION DEFINED configuration and control options for execution at EL1 and EL0.

Note

Arm recommends the contents of this register have no effect on the PE when the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, and instead the configuration and control fields are provided by the ACTLR_EL2 register. This avoids the need for software to manage the contents of these register when switching between a Guest OS and a Host OS.

Configuration

AArch64 System register ACTLR_EL1 bits [31:0] are architecturally mapped to AArch32 System register ACTLR[31:0].

AArch64 System register ACTLR_EL1 bits [63:32] are architecturally mapped to AArch32 System register ACTLR2[31:0].

Attributes

ACTLR_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
IMPLEMENTATION DEFINED
IMPLEMENTATION DEFINED

IMPLEMENTATION DEFINED, bits [63:0]

IMPLEMENTATION DEFINED.

The reset behavior of this field is:

Accessing ACTLR_EL1

If the IMPLEMENTATION DEFINED ACTLR_EL12 accessor is implemented, the following behaviors are also implemented:

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, ACTLR_EL1

op0op1CRnCRmop2
0b110b0000b00010b00000b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TACR == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'1x1'} && (!boolean IMPLEMENTATION_DEFINED "IMPLEMENTED_ACTLR_ELx accessor behavior" || EffectiveHCR_EL2_NVx() == '111') then X[t, 64] = NVMem[0x118]; else X[t, 64] = ACTLR_EL1; elsif PSTATE.EL == EL2 then if boolean IMPLEMENTATION_DEFINED "IMPLEMENTED_ACTLR_ELx accessor behavior" && ELIsInHost(EL2) then X[t, 64] = ACTLR_EL2; else X[t, 64] = ACTLR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = ACTLR_EL1;

MSR ACTLR_EL1, <Xt>

op0op1CRnCRmop2
0b110b0000b00010b00000b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TACR == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'1x1'} && (!boolean IMPLEMENTATION_DEFINED "IMPLEMENTED_ACTLR_ELx accessor behavior" || EffectiveHCR_EL2_NVx() == '111') then NVMem[0x118] = X[t, 64]; else if IsFeatureImplemented(FEAT_SRMASK) then ACTLR_EL1 = (X[t, 64] AND NOT EffectiveACTLRMASK_EL1()) OR (ACTLR_EL1 AND EffectiveACTLRMASK_EL1()); else ACTLR_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if boolean IMPLEMENTATION_DEFINED "IMPLEMENTED_ACTLR_ELx accessor behavior" && ELIsInHost(EL2) then if IsFeatureImplemented(FEAT_SRMASK) then ACTLR_EL2 = (X[t, 64] AND NOT EffectiveACTLRMASK_EL2()) OR (ACTLR_EL2 AND EffectiveACTLRMASK_EL2()); else ACTLR_EL2 = X[t, 64]; else ACTLR_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then ACTLR_EL1 = X[t, 64];

When an implementation implements ACTLR_ELx accessor behavior

MRS <Xt>, ACTLR_EL12

op0op1CRnCRmop2
0b110b1010b00010b00000b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X[t, 64] = NVMem[0x118]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then X[t, 64] = ACTLR_EL1; else UNDEFINED; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X[t, 64] = ACTLR_EL1; else UNDEFINED;

When an implementation implements ACTLR_ELx accessor behavior

MSR ACTLR_EL12, <Xt>

op0op1CRnCRmop2
0b110b1010b00010b00000b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem[0x118] = X[t, 64]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then ACTLR_EL1 = X[t, 64]; else UNDEFINED; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then ACTLR_EL1 = X[t, 64]; else UNDEFINED;

When FEAT_SRMASK is implemented

MRS <Xt>, ACTLRALIAS_EL1

op0op1CRnCRmop2
0b110b0000b00010b01000b101

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TACR == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3.FGTEn2 == '0') || HFGRTR2_EL2.nACTLRALIAS_EL1 == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'1x1'} && (!boolean IMPLEMENTATION_DEFINED "IMPLEMENTED_ACTLR_ELx accessor behavior" || EffectiveHCR_EL2_NVx() == '111') then X[t, 64] = NVMem[0x118]; else X[t, 64] = ACTLR_EL1; elsif PSTATE.EL == EL2 then if boolean IMPLEMENTATION_DEFINED "IMPLEMENTED_ACTLR_ELx accessor behavior" && ELIsInHost(EL2) then X[t, 64] = ACTLR_EL2; else X[t, 64] = ACTLR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = ACTLR_EL1;

When FEAT_SRMASK is implemented

MSR ACTLRALIAS_EL1, <Xt>

op0op1CRnCRmop2
0b110b0000b00010b01000b101

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TACR == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3.FGTEn2 == '0') || HFGWTR2_EL2.nACTLRALIAS_EL1 == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'1x1'} && (!boolean IMPLEMENTATION_DEFINED "IMPLEMENTED_ACTLR_ELx accessor behavior" || EffectiveHCR_EL2_NVx() == '111') then NVMem[0x118] = X[t, 64]; else if IsFeatureImplemented(FEAT_SRMASK) then ACTLR_EL1 = (X[t, 64] AND NOT EffectiveACTLRMASK_EL1()) OR (ACTLR_EL1 AND EffectiveACTLRMASK_EL1()); else ACTLR_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if boolean IMPLEMENTATION_DEFINED "IMPLEMENTED_ACTLR_ELx accessor behavior" && ELIsInHost(EL2) then if IsFeatureImplemented(FEAT_SRMASK) then ACTLR_EL2 = (X[t, 64] AND NOT EffectiveACTLRMASK_EL2()) OR (ACTLR_EL2 AND EffectiveACTLRMASK_EL2()); else X[t, 64] = ACTLR_EL2; else ACTLR_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then ACTLR_EL1 = X[t, 64];


15/12/2024 22:27; 5e0a212688c6bd7aee92394b6f5e491b4d0fee1d

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